View TMP88CP34F_38067.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

TMP88CS34/CP34
CMOS 8-Bit Microcontroller
TMP88CS34N/F, TMP88CP34N/F
The TMP88CS34/CP34 is the high speed and high performance 8-bit single chip microcomputers. This MCU contain CPU core, ROM, RAM, input/output ports, four Multi-function timer/counters, serial bus interface, on-screen display, PWM output, 8-bit AD converter, and remote control signal preprocessor on chip. Product No.
TMP88CS34N/F TMP88CP34N/F
ROM
64 K 48 K 8-bit 8-bit
RAM
1.5 K 8-bit
Package
P-SDIP42-600-1.78 P-QFP44-1414-0.80D
OTP MCU
TMP88PS34N/F
Features
8-bit single chip microcomputer TLCS-870/X Series Instruction execution time: 0.25 s (at 16 MHz) 842 basic instructions Multiplication and Division (8 bits 8 bits, 16 bits 8 bits, 16 bits/8 bits) Bit manipulations (Set/Clear/Complement/Move/Test/Exclusive or) 16-bit data and 20-bit data operations 1-byte jump/subroutine-call (Short relative jump/Vector call) I/O ports: Maximum 33 (High current output: 4) 15 interrupt sources: External 6, Internal 10 All sources have independent latches each, and nested interrupt control is available. Edge-selectable external interrupts with noise reject High-speed task switching by register bank changeover ROM corrective function Two 16-bit timer/counters: TC1, TC2 Timer, Event-counter, Pulse width measurement, External trigger timer, Window modes Two 8-bit timer/counters: TC3, TC4 Timer, Event counter, Capture (Pulse width/duty measurement) mode
000707EBP1
For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance / Handling Precautions. TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. The products described in this document are subject to the foreign exchange and foreign trade laws. The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. The information contained herein is subject to change without notice.
Purchase of TOSHIBA I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
88CS34-1
2003-03-25
TMP88CS34CP34
Time base timer (Interrupt frequency: 0.95 Hz to 31250 Hz) Watchdog timer Interrupt source/reset output Serial bus interface I2C bus, 8-bit SIO mode (Selectable two I/O channels) On-screen display circuit Font ROM characters: Mono font 383 characters, color font 96 characters or mono font 447 characters, color font 64 characters Characters display: 32 columns 12 lines Composition: 16 18 dots Size of character: 4 kinds (line by line) Color of character: 8 or 27 kinds (character by character) Variable display position: Horizontal 256 steps, Vertical 625 steps Fringing, Smoothing, Slant, Underline , Blinking function Jitter elimination DA conversion (Pulse Width Modulation) outputs 14/12-bit resolution (2 channels) 12-bit resolution (2 channels) 8-bit successive approximate type AD converter with sample and hold High current output: 1 pin (typ. 20 mA) Remote control signal preprocessor Two power saving operating modes STOP mode: Oscillation stops. Battery/Capacitor back-up. Port output hold/high-impedance. IDLE mode: CPU stops, and Peripherals operate using high-frequency clock. Release by interrupts. Operating voltage: 4.5 to 5.5 V at 16 MHz Emulation POD: BM88CS34N0A-M15
88CS34-2
2003-03-25
TMP88CS34CP34
Pin Assignments
Package P-SDIP42-600-1.78 P-SDIP42-600-1.78 VSS ( PWM0 ) P40 ( PWM1 ) P41 ( PWM2 ) P42 ( PWM3 ) P43 P44 P45 P46 P47 (TC2/ INT0 ) P50 (SI1/SCL1) P51 (SO1/SDA1) P52 ( KWU0 / SCK1 /INT2/TC1/AIN0) P53 ( KWU1 /AIN1) P54 ( KWU2 /AIN2) P55 ( KWU3 /AIN3) P56 ( KWU4 /Y/BLIN/AIN4) P60 ( KWU5 /BIN/AIN5) P61 (GIN) P62 (RIN) P63 (I) P57 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 VDD P33 (TC4) P32 VVSS P35 (SDA0) P34 (SCL0) P31 (INT4/TC3) P30 (INT3/RXIN) P20 ( INT5 / STOP )
RESET
TMP88CS34N TMP88CP34N TMP88PS34N
XOUT XIN TEST OSC2 OSC1 P71 ( VD ) P70 ( HD ) P67 (Y/BL) P66 (B) P65 (G) P64 (R)
Package P-QFP44-1414-0.80D
P-QFP44-1414-0.80D P34 (SCL0) P31 (INT4/TC3) P30 (INT3/RXIN) P20 (INT5/STOP) 34 35 36 37 38 39 40 41 42 43 44
TMP88CS34F TMP88CP34F TMP88PS34F (SDA0) P35 VVSS P32 (TC4) P33 N.C. VDD VSS ( PWM0 ) P40 ( PWM1 ) P41 ( PWM2 ) P42 ( PWM3 ) P43
33 32 31 30 29 28 27 26 25 24 23
XOUT XIN TEST OSC2 OSC1 P71 (VD) 22 21 20 19 18 17 16 15 14 13 12
RESET
P44 P45 P46 P47 (TC2/INT0) P50 (SI1/SCL1) P51 (SO1/SDA1) P52 (KWU0/SCK1/INT2/TC1/AIN0) P53 (KWU1/AIN1) P54 (KWU2/AIN2) P55 (KWU3/AIN3) P56
1 2 3 4 5 6 7 8 9 10 11
P70 ( HD ) P67 (Y/BL) P66 (B) P65 (G) P64 (R) N.C. P57 P63 (RIN) P62 (GIN) P61 (BIN//AIN5/ KWU5 ) P60 (Y/BLIN/AIN4/ KWU4 )
88CS34-3
2003-03-25
TMP88CS34CP34
Pin Functions (1/2)
Pin Name
P20 ( INT5 / STOP ) P35 (SDA0) P34 (SCL0) P33 (TC4) P32 P31 (INT4/TC3) P30 (INT3/RXIN) P47 P46 P45 P44 P43 ( PWM3 ) P42 ( PWM2 ) P41 ( PWM1 ) P40 ( PWM0 ) P57 (I) P56 ( KWU3 /AIN3) P55 ( KWU2 /AIN2) P54 ( KWU1 /AIN1) P53 ( KWU0 /AIN0/TC1 /INT2/ SCK1 )
I/O
I/O (Input) I/O (Input/Output) I/O (Input/Output) I/O (Input) I/O I/O (Input) I/O (Input) I/O I/O I/O I/O I/O (Output) I/O (Output) I/O (Output) I/O (Output) I/O (Output) I/O (Input) I/O (Input) I/O (Input) I/O (Input/Input/Input /Input/Output) I/O (Input/Output/Output) I/O (Input/Output/Input) I/O (Input/Input) I/O (Output) I/O (Output) I/O (Output) I/O (Output) I/O (Input) I/O (Input) I/O (Input) 1-bit input/output port with latch. When used as an input port, the latch must be set to "1".
Function
External interrupt input 5 or STOP mode release signal input I2C bus serial data input/output 0 I2C bus serial clock input/output 0 Video signal input 1 or Composite sync input External interrupt input 4 or Timer/Counter input 3 External interrupt input 3 or Remote control signal preprocessor input 8-bit programmable input/output port. Each bit of these ports can be individually configured as an input or an output under software control. During reset, all bits are configured as inputs.
6-bit programmable input/output port. Each bit of these ports can be individually configured as an input or an output under software control. During reset, all bits are configured as inputs. When used as a serial bus interface input/output, the latch must be set to "1".
12-bit DA conversion (PWM) outputs 14/12-bit DA conversion (PWM) outputs
8-bit programmable input/output port. Each bit of these ports can be individually configured as an input or an output under software control. During reset, all bits are configured as inputs. When used as a serial bus interface input/output, the latch must be set to "1".
Translucent signal output Key on wake-up inputs or AD converter analog inputs Key on wake-up input or AD converter analog input or Timer/counter input 1 or External interrupt input 2 or SIO serial clock input/output 1 I2C bus serial data Input/Output 1 or SIO serial data output 1 I2C bus serial data Input/Output 1 or SIO serial data input 1 Timer/Counter input 2 or External interrupt input 0
P52 (SDA1/SO1) P51 (SCL1/SI1) P50 (TC2/ INT0 ) P67 (Y/BL) P66 (B) P65 (G) P64 (R) P63 (RIN) P62 (GIN) P61 ( KWU5 /BIN/AIN5)
P60 ( KWU4 /YBLIN/AIN4)
I/O (Input)
8-bit programmable input/output port. (P67 to 61: Tri-State, P60: High current output) Each bit of these ports can be individually configured as an input or an output under software control. During reset, all bits are configured as inputs. When used P64 to P67 as port, each bit of the P6 port data selection register (bit 7 to 4 in ORP6S) must be set to "1". P63 to P61 output 0 after a reset. When these dual-function pins are used as ports, be sure to set ORP6S2 to "1".
Y or BL output R/G/B outputs R input G input Key on wake-up input 5 or B input or AD converter analog input 5
Key on wake-up input 4 or Y/BL input or AD converter analog input 4
88CS34-4
2003-03-25
TMP88CS34CP34
Pin Functions (2/2)
Pin Name
P71 ( VD )
I/O
I/O (Input)
Function
2-bit programmable input/output port. Each bit of these ports can be individually configured as an input or an output under software control. During reset, all bits are configured as inputs. Vertical synchronous signal input
P70 ( HD ) XIN, XOUT RESET TEST OSC1, OSC2 VDD, VSS, VVSS
I/O (Input) Input, Output I/O Input Input, Output Power Supply
Horizontal synchronous signal input
Resonator connecting pins. For inputting external clock, XIN is used and XOUT is opened. Reset signal input or watchdog timer output/address-trap-reset output/system-clock-rest output Test pin for out-going test. Be tied to low. Resonator connecting pins for on-screen display circuitry 5 V, 0 V (GND)
88CS34-5
2003-03-25
TMP88CS34CP34
Block Diagram
I/O Ports P64 to P67 P70, 71 P57
OSC Connecting Pins for On-Screen Display OSC1
OSC2
Display Memory
Character ROM
R, G, B, Jitter Y/BL Elimination
VD HD I
On-screen display circuit P6 P7 P5
Power VDD Supply VSS
VVSS
TLCS-870/X CPU core
Data Memory (RAM)
ROM corrective circuit
Reset I/O Test Pin
RESET TEST
System Controller Standby Controller
Interrupt Controller
Program Counter
Resonator Connecting Pins
XIN XOUT
Timing Generator High Clock frequency Generator
Time Base Timer Watchdog Timer
16-bit Timer TC1 TC2
8-bit Timer/Counter
Program Memory (ROM)
TC3
TC4
Inst. Register Inst. Decoder
P2
P4
DA Converter (PWM)
P5
8-bit AD
Key on wake up
P6
Remote control signal
P3
Serial Bus Interface
Y/BLIN RIN GIN BIN
P20 P40 to P47
P50 to P56
P60 to P63
P30 to P35
I/O Ports
88CS34-6
2003-03-25
TMP88CS34/CP34
Operational Description
1.
CPU Core Functions
The CPU core consists of a CPU, a system clock controller, and an interrupt controller. This section provides a description of the CPU core, the program memory, the data memory, the external memory interface, and the reset circuit.
1.1
Memory Address Map
The TMP88CS34/CP34 memory consists of four blocks: ROM, RAM, SFR (Special Function Register), and DBR (Data Buffer Register). They are all mapped to a 1-Mbyte address space. Figure 1.1.1 shows the TMP88CS34/CP34 memory address map. There are 16 banks of the general-purpose register. The register banks are also assigned to the RAM address space.
00000H SFR 0003FH 00040H 000BFH 000C0H 64 bytes 128 bytes 1536 bytes 006BFH 00F80H DBR 00FFFH 04000H 128 bytes
00000H 0003FH 00040H 000BFH 000C0H 1536 bytes 006BFH 00F80H 128 bytes 00FFFH 04000H 64 bytes 128 bytes
RAM
48896 bytes 65280 bytes
13EFFH ROM FFF00H FFF3FH FFF40H FFF7FH FFF80H FFFFFH TMP88CS34 64 bytes 64 bytes 128 bytes
0FEFFH
FFF00H FFF3FH FFF40H FFF7FH FFF80H FFFFFH TMP88CP34 64 bytes 64 bytes 128 bytes
ROM: Read Only Memory includes Program memory, Character data memory for OSD RAM: Random Access Memory includes Data memory, Stack, General-purpose register banks SFR: Special Function Register includes I/O ports, Peripheral hardware control registers, Peripheral hardware status registers System control registers, Interrupt control registers, Program status word DBR: Data Buffer Register includes Control register for on-screen display (OSD) Remote-control-receive control/status registers, ROM correction control registers Test video signal control registers
Figure 1.1.1 Memory Address Map
88CS34-7
2003-03-25
TMP88CS34/CP34
1.2
Program Memory (ROM)
The TMP88CS34 contains a 64-Kbyte program memory (mask ROM) at addresses from 04000 to 13EFFH and FFF00 to FFFFFH. The TMP88CP34 contains a 48-Kbyte program memory (mask ROM) at address from 04000 to 0FEFFH and FFF00 to FFFFFH. Addresses FFF00 through FFFFFH in the program memory are also used for a particular purpose.
1.3
Data Memory (RAM)
The TMP88CS34/CP34 has a 1.5-Kbyte data memory (Static RAM) address from 0040 to 06BFH. The first 128 bytes (addresses 00040 through 000BFH) in the built-in RAM are also available as general-purpose register banks. The general-purpuse registers are mapped in the RAM; therefore, do not clear RAM at the current bank addresses. Example: Clears RAM to "00H" except the bank 0 (TMP88CS34/CP34): LD HL, 0048H ; Sets start address to HL register pair LD A, H ; Sets initial data (00H) to A register LD BC, 0677H ; Sets number of byte to BC register pair SRAMCLR: LD (HL ), A DEC BC JRS F, SRAMCLR Note: The data memory contents become unstable when the power supply is turned on; therefore, the data memory should be initialized by an initialization routine. Note that the general-purpose registers are mapped in the RAM; therefore, do not clear RAM at the current bank addresses.
1.4
System Clock Controller
The system clock controller consists of a clock generator, a timing generator, and a stand-by controller.
Timing generator control register Clock generator XIN High-frequency clock oscillator XOUT 00038H System clocks Clock generator control SYSCR1 00039H SYSCR2 fc Timing generator Stand-by controller TBTCR 00036H
System control registers
Figure 1.4.1 System Clock Controller
88CS34-8
2003-03-25
TMP88CS34/CP34 1.4.1 Clock Generator
The clock generator generates the basic clock which provides the system clocks supplied to the CPU core and peripheral hardware. It contains oscillation circuit: one for the high-frequency clock. The high-frequency (fc) clock can be easily obtained by connecting a resonator between the XIN/XOUT pin, respectively. Clock input from an external oscillator is also possible. In this case, external clock is applied to XIN pin with XOUT pin not connected.
High-frequency clock XIN XOUT XIN XOUT (open)
(a) Crystal/Ceramic resonator
(b) External oscillator
Figure 1.4.2 Examples of Resonator Connection Note: Accurate adjustment of the oscillation frequency: Although hardware to externally and directly monitor the basic clock pulse is not provided, the oscillation frequency can be adjusted by making the program to output fixed frequency pulses to the port while disabling all interrupts and monitoring this pulse. With a system requiring adjustment of the oscillation frequency, the adjusting program must be created beforehand.
1.4.2
Timing Generator
The timing generator generates from the basic clock the various system clocks supplied to the CPU core and peripheral hardware. The timing generator provides the following functions: 1. Generation of main system clock 2. 3. 4. 5. 6. Generation of source clocks for time base timer Generation of source clocks for watchdog timer Generation of internal source clocks for timer/counters TC1 to TC4 Generation of warm-up clocks for releasing STOP mode Generation of a clock for releasing reset output
(1) Configuration of Timing Generator The timing generator consists of a 21-stage divider with a divided-by-3 prescaler, a main system clock generator, and machine cycle counters. During reset and at releasing STOP mode, the prescaler and the divider are cleared to "0", however, the prescaler is not cleared. An input clock to the 7th stage of the divider depends on the operating mode. A divided-by-256 of high-frequency clock (fc/28) is input to the 7th stage of the divider.
88CS34-9
2003-03-25
TMP88CS34/CP34
fm
DV1CK
Machine cycle counters
Machine cycles States
Prescaler High-frequency clock fc
012
S A B Y
Divider
123456
Divider fc/28
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
Reset circuit Stand-by controller Timer/ Counters Watchdog Timer
Time Base Timer fc D1 D0 MK8 MHz FC8OUT JITTA
Figure 1.4.3 Configuration of Timing Generator
CGCR (00030H)
"0"
"0"
DV1CK
"0"
"0"
"0"
"0"
"0"
(Initial value: 0000 0000)
DV1CK Note 1: Note 2:
Selection of input clock to 0: fc/4 the 1'st stage of the divider. 1: fc/8 *: Don't care
R/W
fc: high-frequency clock [Hz]
The all bits except DV1CK are cleared to "0".
Figure 1.4.4 Divider Control Register
FC8CR (00FEEH) D1 1 0 D0 0 0
D1 FC8OUT 1/2 fc 1/1 fc
D0
Read/Write (Initial value: 0000 0010)
Figure 1.4.5 FC8 Control Register
88CS34-10
2003-03-25
TMP88CS34/CP34
(2) Machine Cycle Instruction execution and peripheral hardware operation are synchronized with the main system clock. The minimum instruction execution unit is called a "machine cycle". There are a total of 15 different types of instructions for the TLCS-870/X Series: ranging from 1-cycle instructions which require one machine cycle for execution to 15-cycle instructions which require 15 machine cycles for execution. A machine cycle consists of 4 states (S0 to S3), and each state consists of one main system clock.
1/fc Main System Clock fm State S0 S1 S2 S3 S0 S1 S2 S3
Machine cycle (0.25 s at fc 16 MHz)
Figure 1.4.6 Machine Cycle
1.4.3
Stand-by Controller
The stand-by controller starts and stops the switches the main system clock. These modes are controlled by the system control registers (SYSCR1, SYSCR2). Figure 1.4.7 shows the operating mode transition diagram and Figure 1.4.8 shows the system control registers. Single-clock mode In the single-clock mode, the machine cycle time is 4/fc [s] (0.25 s at fc = 16 MHz). 1. NORMAL mode In this mode, both the CPU core and on-chip peripherals operate using the high-frequency clock. 2. IDLE mode In this mode, the internal oscillation circuit remains active. The CPU and the watchdog timer are halted; however, on-chip peripherals remain active (operate using the high-frequency clock). IDLE mode is started by setting IDLE bit in the system control register 2 (SYSCR2), and IDLE mode is released to NORMAL mode by an interrupt request from on-chip peripherals or external interrupt inputs. When IMF (interrupt master enable flag) is "1" (interrupt enable), the execution will resume upon acceptance of the interrupt, and the operation will return to normal after the interrupt service is completed. When IMF is "0" (interrupt disable), the execution will resume with the instruction which follows IDLE mode start instruction. 3. STOP mode In this mode, the internal oscillation circuit is turned off, causing all system operations to be halted. The internal status immediately prior to the halt is held with the lowest power consumption during this mode. STOP mode is started by setting STOP bit in the system control register 1 (SYSCR1), and STOP mode is released by an input (either level-sensitive or edge-sensitive can be programmably selected) to the STOP pin. After the warming-up period is completed, the execution resumes with the next instruction which follows the STOP mode start instruction.
88CS34-11
2003-03-25
TMP88CS34/CP34
RESET
Reset release Software Interrupt Software
IDLE mode
NORMAL mode
STOP mode
STOP pin input
(a) Single-clock mode Note: NORMAL mode is generically called NORMAL; STOP mode is called STOP; and IDLE mode is called IDLE.
Operating Mode
RESET NORMAL Single-Clock IDLE STOP
Frequency High-frequency Low-frequency
CPU Core
Reset
On-chip Machine Peripherals Cycle Time
Reset 4/fc [s] Operate
Turning on oscillation Turning off oscillation
Turning off oscillation
Operate Halt Halt
Figure 1.4.7 Operating Mode Transition Diagram
88CS34-12
2003-03-25
TMP88CS34/CP34
System Control Register 1 7 6 SYSCR1 (00038H) STOP RELM
5 "0"
4 "1"
3 WUT
2
1
0 (Initial value: 0000 00** )
STOP
STOP mode start
0: CPU core and peripherals remain active 1: CPU core and peripherals are halted (start STOP mode) 0: Edge-sensitive release (Rising Edge) 1: Level-sensitive release ("H" Level) Return to NORMAL mode DV1CK 0 DV1CK 3 3 217/fc 217/fc 215/fc 215/fc 1 R/W
RELM
Release method for STOP mode
WUT
Warming-up time at releasing STOP mode
00 01 10 11
3 3
216/fc 216/fc 214/fc 214/fc
Note 1: Note 2:
Always set bit 5 in SYSCR1 to "0". When STOP mode is released with RESET pin input, a return is made to NORMAL mode regardless of the RETM contents.
Note 3:
fc: High-frequency clock [Hz] *: Don't care
Note 4: Note 5:
Bits 1 and 0 in SYSCR1 are read in as undefined data when a read instruction is executed. Always set bit 4 in SYSCR1 to "1" when STOP mode is started.
System Control Register 2 7 6 SYSCR2 (00039H) "1" "0"
5 "0"
4 IDLE
3
2
1
0 (Initial value: 1000 **** )
IDLE Note 1: Note 2:
IDLE mode start *: Don't care
0: CPU and watchdog timer remain active 1: CPU and watchdog timer are stopped (start IDLE mode)
R/W
Always set bit 7, 6 and 5 in SYSCR2 to "100".
Figure 1.4.8 System Control Registers
88CS34-13
2003-03-25
TMP88CS34/CP34
1.4.4
Operating Mode Control
(1) STOP mode STOP mode is controlled by the system control register 1 (SYSCR1) and the STOP pin input. The STOP pin is also used both as a port P20 and an INT5 (external interrupt input 5) pin. STOP mode is started by setting STOP (bit 7 in SYSCR1 ) to "1". During STOP mode, the following status is maintained. 1. 2. 3. 4. Oscillations are turned off, and all internal operations are halted. The data memory, registers and port output latches are all held in the status in effect before STOP mode was entered. The prescaler and the divider of the timing generator are cleared to "0". The program counter holds the address of the instruction following the instruction which started the STOP mode.
STOP mode includes a level-sensitive release mode and an edge-sensitive release mode, either of which can be selected with RELM (bit 6 in SYSCR1). a. Level-sensitive release mode (RELM 1) In this mode, STOP mode is released by setting the STOP pin high. This mode is used for capacitor back-up when the main power supply is cut off and long term battery back-up. When the STOP pin input is high, executing an instruction which starts the STOP mode will not place in STOP mode but instead will immediately start the release sequence (warm-up). Thus, to start STOP mode in the level-sensitive release mode, it is necessary for the program to first confirm that the STOP pin input is low. The following method can be used for confirmation: Using an external interrupt input INT5 ( INT5 is a falling edge-sensitive input). Example: Starting STOP mode with an INT5 interrupt. PINT5: TEST (P2) . 0 ; To reject noise, the STOP mode does not JRS F, SINT5 start if port P20 is at high LD (SYSCR1), 01010000B ; Sets up the level-sensitive release mode. SET (SYSCR1) . 7 ; Starts STOP mode LDW (IL), 1110011101010111B ; IL12, 11, 7, 5, 3 0 (Clears interrupt latches) SINT5: RETI
STOP pin
VIH
XOUT pin NORMAL operation STOP operation Confirm by program that the STOP pin input is low and start STOP mode. Warm-up NORMAL operation
STOP mode is released by the hardware. Always released if the STOP pin input is high.
Note 1: Note 2:
After warming up is started, when STOP pin input is changed "L" level, STOP mode is not placed. When changing to the level-sensitive release mode from the edge-sensitive release mode, the release mode is not switched until a rising edge of the STOP pin input is detected.
Figure 1.4.9 Level-sensitive Release Mode
88CS34-14
2003-03-25
TMP88CS34/CP34
b. Edge-sensitive release mode (RELM 0)
In this mode, STOP mode is released by a rising edge of the STOP pin input. This is used in applications where a relatively short program is executed repeatedly at periodic intervals. This periodic signal (for example, a clock from a low-power consumption oscillator) is input to the STOP pin. In the edge-sensitive release mode, STOP mode is started even when the STOP pin input is high. Example: Starting STOP mode from NORMAL mode LD (SYSCR1), 10010000B ; Starts after specified to the edge-sensitive mode
STOP pin
VIH
XOUT pin NORMAL operation STOP mode started by the program. STOP operation Warm-up STOP operation
NORMAL operation
STOP mode is released by the hardware at the rising edge of STOP pin input.
Figure 1.4.10 Edge-sensitive Release Mode STOP mode is released by the following sequence: 1. 2. When returning to NORMAL, clock oscillator is turned on. A warming-up period is inserted to allow oscillation time to stabilize. During warm-up, all internal operations remain halted. Two different warming-up times can be selected with WUT (bits 2 and 3 in SYSCR1) as determined by the resonator characteristics. When the warming-up time has elapsed, normal operation resumes with the instruction following the STOP mode start instruction (e.g. [SET (SYSCR1). 7]). The start is made after the divider of the timing generator is cleared to "0". Table 1.4.1 Warming-up Time Example Warming-up Time [ms] WUT
00 01 10 11 3 3 2 /fc 216/fc 214/fc 214/fc
16
3.
Return to NORMAL mode DV1CK 0
(12.29) (4.10) (3.07) (1.02) 3 3
DV1CK
2 /fc 217/fc 215/fc 215/fc
17
1
(24.58) (8.20) (6.14) (2.05)
Note: The warming-up time is obtained by dividing the basic clock by the divider: therefore, the warming-up time may include a certain amount of error if there is any fluctuation of the oscillation frequency when STOP mode is released. Thus, the warming-up time must be considered an approximate value.
88CS34-15
2003-03-25
Turn off
Oscillator circuit
Turn on
Main system clock a SET (SYSCR1). 7 n 1 n 2 n 3 n 4 2 a 3 Halt
Program counter
Instruction execution
Divider
n
0
(a) STOP Mode Start (Example: Start with SET (SYSCR1). 7 instruction located at address a)
Warming up
Figure 1.4.11 STOP Mode Start/Release
a 3 a 4
Instruction at address a 2
88CS34-16
Count up 0 (b) STOP Mode Release 1
STOP pin
input
Turn on
Oscillator Turn circuit off Main system clock Program counter
a
5
Instruction at address a 3
a
6
Instruction at address a 4
Instruction Halt execution
Divider
0
2
3
TMP88CS34/CP34
2003-03-25
TMP88CS34/CP34
STOP mode can also be released by setting the RESET pin low, which immediately performs the normal reset operation. Note: When STOP mode is released with a low hold voltage, the following cautions must be observed. The power supply voltage must be at the operating voltage level before releasing STOP mode. The RESET pin input must also be high, rising together with the power supply voltage. In this case, if an external time constant circuit has been connected, the RESET pin input voltage will increase at a slower rate than the power supply voltage. At this time, there is a danger that a reset may occur if input voltage level of the RESET pin drops below the non-inverting high-level input voltage (hysteresis input).
(2) IDLE mode IDLE mode is controlled by the system control register 2 and maskable interrupts. The following status is maintained during IDLE mode. 1. 2. 3. Operation of the CPU and watchdog timer is halted. On-chip peripherals continue to operate. The data memory, CPU registers and port output latches are all held in the status in effect before IDLE mode was entered. The program counter holds the address of the instruction following the instruction which started IDLE mode. Example: Starting IDLE mode. SET (SYSCR2) . 4
;
IDLE
1
Starting IDLE mode by instruction CPU, WDT are halted
Reset input No (high) No Normal release mode No IMF Interrupt request Yes 1
Yes
Reset
Yes (Interrupt release mode) Interrupt processing
Execution of the instruction which follows the IDLE mode start instruction
Figure 1.4.12 IDLE Mode
88CS34-17
2003-03-25
TMP88CS34/CP34
IDLE mode includes a normal release mode and an interrupt release mode. Selection is made with the interrupt master enable flag (IMF). Releasing the IDLE mode returns from IDLE to NORMAL. a. Normal release mode (IMF "0")
IDLE mode is released by any interrupt source enabled by the individual interrupt enable flag (EF) or an external interrupt 0 ( INT0 pin) request. Execution resumes with the instruction following the IDLE mode start instruction (e.g. [SET (SYSCR2).4]). Normally, IL (Interrupt Latch) of interrupt source to release IDLE mode must be cleared by load instructions. b. Interrupt release mode (IMF "1")
IDLE mode is released and interrupt processing is started by any interrupt source enabled with the individual interrupt enable flag (EF) or an external interrupt 0 ( INT0 pin) request. After the interrupt is processed, the execution resumes from the instruction following the instruction which started IDLE mode.
Note:
When a watchdog timer interrupt is generated immediately before the IDLE mode is started, the watchdog timer interrupt will be processed but IDLE mode will not be started.
88CS34-18
2003-03-25
Main system clock
Interrupt request a SET (SYSCR2). 4 Operate (a) IDLE Mode Start (Example: starting with the SET instruction located at address a) Halt 2 a 3
Program counter
Instruction execution
Watchdog timer
Main system clock
Interrupt request a Instruction at address a Operate (I) Normal Release Mode 2 3 a 4
Figure 1.4.13 IDLE Mode Start/Release
a 3 Acceptance of interrupt Operate (II) Interrupt Release Mode (b) IDLE Mode Release
88CS34-19
Program counter
Instruction execution
Halt
Watchdog timer
Halt
Main system clock
Interrupt request
Program counter
Instruction execution
Halt
TMP88CS34/CP34
Watchdog timer
2003-03-25
Halt
TMP88CS34/CP34
IDLE mode can also be released by setting the RESET pin low, which immediately performs the reset operation. After reset, the TMP88CS34/CP34 is placed in NORMAL mode.
88CS34-20
2003-03-25
TMP88CS34/CP34
1.5
Interrupt Controller
The TMP88CS34/CP34 has a total of 16 interrupt sources; 6 externals and 10 internals. Multiple interrupts with priorities are also possible. Two of the internal sources are pseudo non-maskable interrupts; the remainder are all maskable interrupts. Interrupt sources are provided with interrupt latches (IL), which hold interrupt requests, and independent vectors. The interrupt latch is set to "1" by the generation of its interrupt request which requests the CPU to accept its interrupts. Interrupts are enabled or disabled by software using the interrupt master enable flag (IMF) and interrupt enable flag (EF). If more than one interrupts are generated simulaneously, interrupts are accepted in order which is dominated by hardware. However, there are no prioritized interrupt factors among non-maskable interrupts. Table 1.5.1 Interrupt Sources Interrupt source Enable condition
Non-Maskable (Software interrupt) (Watchdog timer interrupt) (External interrupt 0) (16-bit TC1 interrupt) (Key-On-Wake-Up) (Time base timer interrupt) (External interrupt 2) (8-bit TC3 interrupt) (SBI interrupt) (8-bit TC4 interrupt) (External interrupt 3) (External interrupt 4) (AD Converter interrupt) (16-bit TC2 interrupt) (External interrupt 5) (OSD interrupt) Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Pseudo non-maskable IMF IMF IMF IMF IMF IMF IMF IMF IMF IMF IMF IMF IMF IMF IMF IMF IMF IMF IMF IMF IMF IMF IMF IMF IMF IMF IMF IMF IMF EF3 EF4 EF5 EF6 EF7 EF8 EF9 EF10 EF11 EF12 EF13 EF14 EF15 EF16 EF17 EF18 EF19 EF20 EF21 EF22 EF23 EF24 EF25 EF26 EF27 EF28 EF29 EF30 EF31 1, INT0EN 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Interrupt latch
Vector table address
FFFFCH FFFF8H FFFF4H FFFF0H FFFECH FFFE8H FFFE4H FFFE0H FFFDCH FFFD8H FFFD4H FFFD0H FFFCCH FFFC8H FFFC4H FFFC0H FFFBCH FFFB8H FFFB4H FFFB0H FFFACH FFFA8H FFFA4H FFFA0H FFF9CH FFF98H FFF94H FFF90H FFF8CH FFF88H FFF84H FFF80H
Priority
High 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Low 31
Internal/ External Internal Internal External Internal External Internal External Internal Internal Internal External External Internal Internal External Internal
(Reset) INTSW INTWDT INT0 INTTC1 INTKWU INTTBT INT2 INTTC3 INTTSBI INTTC4 INT3 INT4 INTADC INTTC2 INT5 INTOSD
IL2 IL3 IL4 IL5 IL6 IL7 IL8 IL9 IL10 IL11 IL12 IL13 IL14 IL15 IL16 IL17 IL18 IL19 IL20 IL21 IL22 IL23 IL24 IL25 IL26 IL27 IL28 IL29 IL30 IL31
Note : Before you change each enable flag (EF) and/or each interrupt latch (IL), be sure to clear the interrupt master enable flag (IMF) to "0" (to disable interrupts). 1. After a DI instruction is executed. 2. When an interrupt is accepted, IMF is autamatically cleared to "0". However, to enable nested interrupts change EF and/or IL before setting IMF to "1" (to enable interrupts). If the individual enable flags (EF) and interrupts (IL) are set under conditions other than the above, proper operation cannot be guararteed.
88CS34-21
2003-03-25
IL16 to IL2 Interrupt latch S IL Q R2 Digital noise reject circuit S IL Q R3 S Q IL R4 S Q IL R5 Priority encoder Vector table address Vector table address generator Non-maskable interrupts request Interrupt request Maskable interrupts Release IDLE mode request request S Q IL R 16 Interrupt acceptance &
INTSW INTWDT
INT0
INT0EN
INTTC1
INTKOW
Figure 1.5.1 Interrupt Controller Block Diagram
IL31 to 3 write data
Write strobe for IL Internal reset
88CS34-22
EF31 to EF3
Interrupt enable flag
INTOSD
Q IMF RS Interrupt master enable flag [RETI] instruction during maskable interrupt service
[DI] Instruction Instruction which clears IMF to "0"
EINTCR
External interrupts control register
[RETN] instruction only when IMF was set before interrupt was accepted [EI] instruction Instruction which sets IMF to "1"
TMP88CS34/CP34
2003-03-25
TMP88CS34/CP34
Interrupt latches (IL) that hold the interrupt requests are provided for interrupt sources. Each interrupt vector is independent. The interrupt latch is set to "1" when an interrupt request is generated, and requests the CPU to accept the interrupt. The acceptance of maskable interrupts can be selectively enabled and disabled by program using the interrupt master enable flag (IMF) and the individual interrupt enable flags (EF). When two or more interrupts are generated simultaneously, the interrupt is accepted in the highest priority order as determined by the hardware. Figure 1.5.1 shows the interrupt controller. (1) Interrupt Latches (IL31 to IL2) Interrupt latches are provided for each source, except for a software interrupt. The latch is set to "1" when an interrupt request is generated, and requests the CPU to accept the interrupt. The latch is cleared to "0" just after the interrupt is accepted. All interrupt latches are initialized to "0" during reset. The interrupt latches are assigned to addresses 0003CH, 0003DH, 0002EH and 0002FH in the SFR. Except for IL2, each latch can be cleared to "0" individually by an instruction; however, the read-modify-write instruction such as bit manipulation or operation instructions cannot be used. When interrupt occurred during order execution, the reason is because interrupt request is cleared. Thus, interrupt requests can be canceled and initialized by the program. Note that request the interrupt latches cannot be set to "1" by an instruction. For example, it may be that each latch is cleared even if an interrupt request is generated during instruction exection. The contents of interrupt latches can be read out by an instruction. Therefore, testing interrupt request by software is possible. Example 1: Clears interrupt latches LDW (ILL), 1110100000111111B Example 2: Reads interrupt latches LD WA, (ILL) Example 3: Tests an interrupt latch TEST (ILL). 7 JR F, SSET (2) Interrupt Enable Register (EIR) The interrupt enable register (EIR) enables and disables the acceptance of interrupts, except for the pseudo non-maskable interrupts (software and watchdog timer interrupts). Pseudo non-maskable interrupts are accepted regardless of the contents of the EIR; however, the pseudo non-maskable interrupt cannot be nested more than once at the same time. The EIR consists of an interrupt master enable flag (IMF) and the individual interrupt enable flags (EF). These registers are assigned to addresses 0003AH, 0003BH, 0002CH and 0002DH in the SFR, and can be read and written by an instruction (including read-modify-write instruction such as bit manipulation instructions). Note: Do not use the read-modify-write instruction for the EIRL (address 0003AH) during pseudo non-maskable interrupt service task. If the read-modify-write instruction is used, the IMF is not set to "1" after RETN. ; ; ; IL12, IL10 to IL6 W if IL7 ILH, A ILL 0
1 then jump
88CS34-23
2003-03-25
TMP88CS34/CP34
1. Interrupt Master enable Flag (IMF) The interrupt master enable flag (IMF) enables and disables the acceptance of all maskable interrupts. Clearing this flag to "0" disables the acceptance of all maskable interrupts. Setting to "1" enables the acceptance of interrupts. When an interrupt is accepted, this flag is cleared to "0" to temporarily disable the acceptance of other maskable interrupts. After execution of the interrupt service program, this flag is set to "1" by the maskable interrupt return instruction [RETI] to again enable the acceptance of interrupts. If an interrupt request has already been occurred, interrupt service starts immediately after execution of the [RETI] instruction. Pseudo non-maskable interrupts are returned by the [RETN] instruction. In this case, the IMF is set to "1" only when pseudo non-maskable interrupt service is started with interrupt acceptance enabled (IMF 1). Note that the IMF remains "0" when cleared by the interrupt service program. The IMF is assigned to bit 0 at address 0003AH in the SFR, and can be read and written by an instruction. The IMF is normally set and cleared by the [EI] and [DI] instructions, and the IMF is initialized to "0" during reset. 2. Individual interrupt Enable Flags (EF16 to EF3) These flags enable and disable the acceptance of individual maskable interrupts, except for an external interrupt 0. Setting the corresponding bit of an individual interrupt enable flag to "1" enables acceptance of an interrupt, setting the bit to "0" disables acceptance. Example 1: Sets EF for individual interrupt enable, and sets IMF to "1". LD (EIRE), 00000001B ; EF16 1 LDW (EIRL), 1110100010100001B EF15 to EF13, EF11, EF7, EF5, IMF Example 2: Sets an individual interrupt enable flag to "1". SET (EIRH). 4 ; EF12 1
1
88CS34-24
2003-03-25
TMP88CS34/CP34
Interrupt Latches (IL)
IL (0002E, 0002FH) 15 IL31 14 IL30 13 IL29 12 IL28 11 IL27 10 IL26 9 IL25 8 IL24 7 IL23 6 IL22 5 IL21 4 IL20 3 IL19 2 IL18 1 IL17 0 IL16
ILD (0002FH) IL (0003C, 0003DH)
ILE (0002EH) (Initial value: 00000000 IL10 IL9 IL8 IL7 IL6 IL5 IL4 IL3 IL2
00000000) INF
IL15
IL14
IL13
IL12
IL11
ILH (0003DH)
ILE (0003CH) (Initial value: 00000000
000000**)
Interrupt Enable Registers (EIR)
EIR (0002C, 0002DH) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EF31 EF30 EF29 EF28 EF27 EF26 EF25 EF24 EF23 EF22 EF21 EF20 EF19 EF18 EF17 EF16 EIRD (0002DH) EIR (0003A, 0003BH) EIRE (0002CH) (Initial value: 00000000 EF9 EF8 EF7 EF6 EF5 EF4 EF3 00000000) IMF
EF15 EF14 EF13 EF12 EF11 EF10 EIRH (0003BH) Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7:
EIRL (0003AH) (Initial value: 00000000 00000**0)
Do not clear IL with read-modify-write instructions such as bit operations. Do not set IMF to "1" during non-maskable interrupt service program. Bits 1 and 0 in ILL are read in as undefined data when a read instruction is executed. *: Don't care Do not clear IL2 to "0" by an instruction. At TMP88CS34/CP34, IL17 to IL31 and IF17 to IF31 are not used. After IMF is cleared, modify EF and IL.
Figure 1.5.2 Interrupt Latches (IL) and Interrupt Enable Registers (EIR)
1.5.1
Interrupt Sequence
An interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to "0" by a reset or an instruction. Interrupt acceptance sequence requires 12 machine cycles (3 s at fc 16 MHz in the NORMAL mode) after the completion of the current instruction execution. The interrupt service task terminates upon execution of an interrupt return instruction [RETI] (for maskable interrupts) or [RETN] (for pseudo non-maskable interrupts). Figure 1.5.3 shows the timing chart of interrupt acceptance processing.
(1) Interrupt acceptance Interrupt acceptance processing is as follows. 1. The interrupt master enable flag (IMF) is cleared to "0" to temporarily disable the acceptance of any following maskable interrupts. When a non-maskable interrupt is accepted, the acceptance of any following interrupts is temporarily disabled. The interrupt latch (IL) for the interrupt source accepted is cleared to "0". The contents of the program counter (PC) and the program status word (PSW) are saved (pushed) on the stack in sequence of PSWH, PSWL, PCE, PCH, PCL. The stack pointer (SP) is decremented five times. 4. The entry address of the interrupt service program is read from the vector table, and set to the program counter.
2. 3.
88CS34-25
2003-03-25
TMP88CS34/CP34
5. 6. The RBS control code is read from the vector table. The lower 4-bit of this code is added to the RBS. The instruction stored at the entry address of the interrupt service program is executed. Correspondence between vector table address for INTTBT and the entry address of the interrupt service program.
Vector table address Entry address
Example:
FFFE4H FFFE5H FFFE6H FFFE7H
43H D2H 0CH 06H RBS control Vector
CD243H CD244H CD245H CD246H Interrupt service program
A maskable interrupt is not accepted until the IMF is set to "1" even if the maskable interrupt higher than the level of current servicing interrupt is occurred. When nested interrupt service is necessary, the IMF is set to "1" in the interrupt service program. In this case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags. Note: Do not use the read-modify-write instruction for the EIRL (address 0003AH) during pseudo non-maskable interrupt service task.
88CS34-26
2003-03-25
TMP88CS34/CP34
1-machine cycle INT5 INTTBT IL15 IL6 IMF Execution Address bus PC SP RBS INF (a) Interrupt acceptance a Instruction a a 1 n
i
Interrupt service task
Interrupt acceptance a 1
FFFE4 FFFE5 FFFE6 FFFE7
Instruction
n
n
1n
2n
3n
4 b
b b
b 1b n
k i
1b 2b 5
2 3
a n 1n2n 3n 4
(FFFE7H). 3
0
Interrupt service task IMF Execution Address bus PC SP RBS INF (b) Return from interrupt instruction Note1: Note2: a: return address, b: entry address, c: address which the RETI instruction is stored The maximum response time from when an IL is set until an interrupt acceptance processing starts is 62/fc [s] with interrupt enabled. c c c n 1 5 n c 1n 4n c 4n k 3n 2 3n 2n 1 RETI Instruction 2n 1 n a a a a 1a n i 1 2
Figure 1.5.3 Timing Chart of Interrupt Acceptance and Interrupt Return Instruction
88CS34-27
2003-03-25
TMP88CS34/CP34
(2) Saving/Restoring general-purpose registers During interrupt acceptance processing, the program counter (PC) and the program status word (PSW) are automatically saved on the stack, but not the accumulator and other registers. These registers are saved by the program if necessary. Also, when nesting multiple interrupt services, it is necessary to avoid using the same data memory area for saving registers. The following method is used to save/restore the general-purpose registers. 1. General-purpose register save/restore by automatic register bank changeover The general-purpose registers can be saved at high-speed by switching to a register bank that is not in use. Normally, the bank 0 is used for the main task and the banks 1 to 15 are assigned to interrupt service tasks. To increase the efficiency of data memory utilization, the same bank is assigned for interrupt sources which are not nested. The switched bank is automatically restored by executing an interrupt return instruction [RETI] or [RETN]. Therefore, it is not necessary for a program to save the RBS. Example: Register bank changeover PINTxx: interrupt processing RETI VINTxx: DP DB PINTxx 1
;
RBS
RBS
1
2.
General-purpose register save/restore by register bank changeover The general-purpose registers can be saved at high-speed by switching to a register bank that is not in use. Normally, the bank 0 is used for the main tank and the banks 1 to 15 are assigned to interrupt service tasks. Example: Register bank changeover PINTxx: LD RBS, n interrupt processing RETI ; VINTxx: DP DB PINTxx 0 ;
Restores bank and Returns Interrupt service routine entry address
Main task Bank m Acceptance of interrupt Interrupt service task m n
Switch to bank n by LD, RBS and n instruction Switch to bank n automatically Restore to bank m automatically by [RETI]/[RETN]
Main task m Acceptance of interrupt Interrupt service task Saving registers
Time
m
Interrupt return
Restoring registers Interrupt return
(a) Saving/Restoring by register bank changeover
(b) Saving/Restoring using push/pop or data transfer instructions
Figure 1.5.4 Saving/Restoring General-purpose Registers
88CS34-28
2003-03-25
TMP88CS34/CP34
3. General-purpose registers save/restore using push and pop instructions To save only a specific register, and when the same interrupt source occurs more than once, the general-purpose registers can be saved/restored using the push/pop instructions. Example: Register save/restore using push and pop instructions PINTxx: PUSH WA ; Save WA register pair interrupt processing POP WA ; Restore WA register pair RETI ; Return
Address (example) SP A SP PCL PCH PCE PSWL PSWH W PCL PCH PCE PSWL PSWH SP PCL PCH PCE PSWL PSWH SP 0023AH 0023B 0023C 0023D 0023E 0023F 00240 00241
At acceptance of an interrupt
At execution of a push instruction
At execution of a pop instruction
At execution of an interrupt return instruction
4.
General-purpose registers save/restore using data transfer instructions Data transfer instruction can be used to save only a specific general-purpose register during processing of single interrupt. Example: Saving/restoring a register using data transfer instructions PINTxx: LD (GSAVA), A ; Save A register interrupt processing LD A, (GSAVA) ; Restore A register RETI ; Return
88CS34-29
2003-03-25
TMP88CS34/CP34
(3) Interrupt return The interrupt return instructions [RETI]/[RETN] perform the following operations. [RETI] Maskable interrupt return
1. The contents of the program counter and the program status word are restored from the stack. 2. The stack pointer is incremented 5 times. 3. The interrupt master enable flag is set to "1".
[RETN] Non-maskable interrupt return
1. The contents of the program counter and program status word are restored from the stack. 2. The stack pointer is incremented 5 times. 3. The interrupt master enable flag is set to "1" only when a non-maskable interrupt is accepted in interrupt enable status. However, the interrupt master enable flag remains at "0" when so clear by an interrupt service program. 4. The interrupt nesting counter is decremented, and the interrupt nesting flag is changed.
4. The interrupt nesting counter is decremented, and the interrupt nesting flag is changed.
Interrupt requests are sampled during the final cycle of the instruction being executed. Thus, the next interrupt can be accepted immediately after the interrupt return instruction is executed. Note: When the interrupt processing time is longer than the interrupt request generation time, the interrupt service task is performed but not the main task.
1.5.2
Software Interrupt (INTSW)
Executing the [SWI] instruction generates a software interrupt and immediately starts interrupt processing (INTSW is highest prioritized interrupt). However, if processing of a non-maskable interrupt is already underway, executing the SWI instruction will not generate a software interrupt but will result in the same operation as the [NOP] instruction. Use the [SWI] instruction only for detection of the address error or for debugging. 1. Address error detection FFH is read if for some cause such as noise the CPU attempts to fetch an instruction from a non-existent memory address. Code FFH is the SWI instruction, so a software interrupt is generated and an address error is detected. The address error detection range can be further expanded by writing FFH to unused areas of the program memory. Address-trap reset is generated in case that an instruction is fetched from RAM, SFR or DBR areas. 2. Debugging Debugging efficiency can be increased by placing the SWI instruction at the software break point setting address.
1.5.3
External Interrupts
The TMP88CS34/CP34 each have five external interrupt inputs ( INT0 , INT2, INT3, INT4, and INT5 ). Three of these are equipped with digital noise rejection circuits (pulse inputs of less than a certain time are eliminated as noise). Edge selection is also possible with INT2, INT3 and INT4. The INT0 /P50 pin can be configured as either an external interrupt input pin or an input/output port, and is configured as an input port during reset. Edge selection, noise rejection control except INT3 pin input and INT0 /P50 pin function selection are performed by the external interrupt control register (EINTCR). Edge selecting and noise rejection control for INT3 pin input are preformed by the Remote control signal preprocessor control registers. (refer to the section of the Remote control signal preprocessor.) When INT0EN pin input is detected. 0, the IL3 will not be set even if the falling edge of INT0
88CS34-30
2003-03-25
TMP88CS34/CP34
Table 1.5.1 External Interrupts Source Pin Secondary function pin Enable conditions Edge Digital noise rejection
Any pulse shorter than 2/fc [s] is regarded as noise and removed. Pulses not shorter than 7/fc [s] are definitely regarded as signals. Pulses of less than 7/fc [s] are eliminated as noise. Pulses equal to or more than 25/fc [s] are regarded as signals. Refer to the section of the Remote control preprocessor Pulses of less than 7/fc [s] are eliminated as noise. Pulses of 25/fc [s] or more are considered to be signals. Any pulse shorter than 2/fc [s] is regarded as noise and removed. Pulse not shorter than 7/fc [s] are definitely regarded as signals.
INT0
INT0
P50/TC2
IMF
1, INT0EN
1, EF3
1
Falling edge
P53/TC1/ INT2 INT2
SCK1
/AIN0/
KWU0
IMF EF7
1
Falling edge or Rising edge Falling edge, Rising edge or Falling/Rising edge Falling edge or Rising edge
INT3
INT3
P30/RXIN
IMF EF11
1
INT4
INT4
P31/TC3
IMF EF12
1
INT5
INT5
P20/ STOP
IMF EF15
1
Falling edge
Note 1: The noise rejection function is also affected for timer/counter input (TC1 pin). Note 2: If a noiseless signal is input to the external interrupt pin in the NORMAL or IDLE mode, the maximum time from the edge of input signal until the IL is set is as follows: (1) INT2, INT4 pin 31/fc [s] (2) INT3 pin Refer to the section of the Remote control preprocessor. Note 3: If a dual-function pin is used as an output port, changing data or switching between input and output generates a pseudo interrupt request signal. To ignore this signal, it is necessary to reset the interrupt enable flag. Note 4: If INT0EN "0", detecting the falling edge of the INT0 pin input does not set the interrupt latch IL3.
88CS34-31
2003-03-25
TMP88CS34/CP34
EINTCR (00037H)
7 "0"
6 INT0 EN
5
4 INT4 ES
3
2 INT2 ES
1 "0"
0 (Initial value: 00*0 *00*)
INT0EN INT4ES INT2ES Note 1: Note 2: Note 3:
P50/ INT0 pin configuration INT4 and INT2 edge select
0: P50 input/output port 1: INT0 pin (Port P50 should be set to an input mode) 0: Rising edge 1: Falling edge
Write only
fc: High-frequency clock [Hz], *: Don't care Edge detection during switching edge selection is invalid. Do not change EINTCR only when IMF 1. After changing EINTCR, interrupt latches of external interrupt
inputs must be cleared to "0" using load instruction. Note 4: In order to change of external interrupt input by rewriting the contents of INT2ES and INT4ES during NORMAL mode, clear interrupt latches of external interrupt inputs (INT2 and INT4) after 8 machine cycles from the time of rewriting. Note 5: In order to change an edge of timer counter input by rewritng the contents of INT2ES during NORMAL mode, rewrite the contents after timer counter is stopped (TC*s 0) , that is, interrupt disable state.
Then, clear a interrupt latch of external interrupt input (INT2) after 8 machine cycles from the time of rewriting to change to interrupt enable state. Finally, start timer counter. Example: When changing TC1 pin inputs edge in external trigger timer mode from rising edge falling edge. LD (TC1CR), 01001000B ; TC1S 00 (stops TC1) DI ; IMF 0 (disables interrupt service) LD (EINTCR), 00000100B ; INT2ES 1 (change edge selection) NOP 8-machine to cycles NOP LD (ILL), 01111111B ; IL7 0 (clears interrupt latch) EI ; IMF 1 (enables interrupt service) LD (TC1CR), 01111000B ; TC1S 11 (starts TC1)
Figure 1.5.5 External Interrupt Control Register
88CS34-32
2003-03-25
TMP88CS34/CP34
1.6
Reset Circuit
The TMP88CS34/CP34 has four types of reset generation procedures: an external reset input, an address trap reset output, a watchdog timer reset output and a system clock reset output. Table 1.6.1 shows on-chip hardware initialization by reset action. The malfunction reset output circuit such as watchdog timer reset, address trap reset and system clock reset is not initialized when power is turned on. The RESET pin can output level "L" at the maximum 24/fc [s] (1.5 s at 16 MHz) when power is turned on. Table 1.6.1 Initializing Internal Status by Reset Action On-chip hardware Initial value
(PC) (SP) (FFFFEH to FFFFCH) not initialized not initialized 0 1 Not initialized Not initialized Not initialized Not initialized Not initialized 0 0 (EF) Control registers 0 RAM (IL) Refer to each of control register Not initialized Output latches of I/O ports Refer to I/O port circuitry Prescaler and Divider of timing generator 0
On-chip hardware
Initial value
Program counter Stack pointer
General-purpose registers (W, A, B, C, D, E, H, L) Register bank selector Jump status flag Zero flag Carry flag Half carry flag Sign flag Overflow flag Interrupt master enable flag Interrupt individual enable flags Interrupt latches (RBS) (JF) (ZF) (CF) (HF) (SF) (VF) (IMF)
Watchdog timer
Enable
1.6.1
External Reset Input
The RESET pin contains a Schmitt trigger (hysteresis) with an internal pull-up resistor. When the RESET pin is held at "L" level for at least 3 machine cycles (12/fc [s]) with the power supply voltage within the operating voltage range and oscillation stable, a reset is applied and the internal state is initialized. When the RESET pin input goes high, the reset operation is released and the program execution starts at the vector address stored at addresses FFFFCH to FFFFEH.
VDD
RESET
Reset input Watchdog timer reset Malfunction reset output circuit Address trap reset System clock reset
Sink open drain
Figure 1.6.1 Reset Circuit
88CS34-33
2003-03-25
TMP88CS34/CP34 1.6.2 Address-Trap-Reset
If the CPU should start looping for some cause such as noise and an attempt be made to fetch an instruction from the on-chip RAM, DBR or the SFR area, address-trap-reset will be generated. Then, the RESET pin output will go low. The reset time is about 8/fc to 24/fc [s] (0.5 to 1.5 s at 16 MHz).
Instruction execution
RESET output
JP
a Address-trap is occurred ("L" output)
Reset release
Instruction at address
(High-Z)
8/fc to 24/fc [s]
4/fc to 12/fc [s]
20/fc [s] (No wait)
Note 1:
Letter "a" represents an address in the built-in RAM, SFR, or DBR area. If the ROM corrective function is enabled, no address trap occurs in a RAM area of 002C0H to 06BFH. If the ROM corrective function is disabled, an address trap occurs in the following area: 00000H a 00FFFH
If the ROM corrective function is enabled, an address trap occurs in the following area: 00000H Note 2: a 002BFH or 006C0H a 00FFFH
During reset release, reset vector "r" is read out, and an instruction at address "r" is fetched and decoded.
Figure 1.6.2 Address-Trap-Reset
1.6.3
Watchdog Timer Reset
Refer to Section "2.4 Watchdog Timer".
1.6.4
System-Clock-Reset
Clearing bits 7 in SYSCR2 to "0", system clock stops and causes the microcomputer to deadlock. This can be prevented by automatically generating a reset signal whenever bits 7, 6 and 5 in SYSCR2 000 is detected to continue the oscillation. The RESET pin output goes low from high-impedance. The reset time is about 8/fc to 24/fc [s] (0.5 to 1.5 s at 16 MHz).
88CS34-34
2003-03-25
TMP88CS34/CP34
1.7
ROM Corrective Function
The ROM corrective function can patch the part (s) of on-chip ROM with some bugs. The ROM corrective function have two modes. One is to replaced the instruction on a certain address in the ROM with the jump instruction to branch into the RAM area where the patched codes (Program Jump Mode). The other is to replace a byte or a word (2 or 3 bytes) length data in the ROM with the patched data (Data Replacement Mode). Four independent location can be patched. Note 1: When use ROM corrective circuit, it is necessary to contain a program which operates to load patched program and/or replacement data from external memory into an internal data RAM in an initial routine. Note 2: The address of an instruction for IDLE mode cannot be specificated as start address of corrective area. Note 3: The BM88CS34N0A-M15 does not support the ROM corrective circuit. Use the TMP88PS34 to debug a program of this circuit. In this case, note the following. Example:
ROM corrective circuit
ROMCDR
ROMCDR
RAM
Serial Bus Interface
Correction mode Correction code Patch program
88CS34-35
2003-03-25
TMP88CS34/CP34 1.7.1 Configuration
BANK0 BANK1 BANK2 BANK3 Address Bus Match Signal Data Bus
Address Compare Circuit 23 to Register 6 Selection 5 Circuit 4 3 2 1 0 5
Instruction Fetch Control Circuit
to
to
the lower the middle the upper Compare Address Register
the lower
the middle the upper Data Register
Corrective Mode Signal Write Data Count Register Write Signal ROMCDR ROM Corrective Data Register WDC Write Data Count Register CM3-0 ROM Corrective Control Register
CM CM CM CM 0123
Figure 1.7.1 ROM Corrective Circuit
88CS34-36
2003-03-25
TMP88CS34/CP34 1.7.2 Control
The ROM corrective function is controlled by ROM corrective control register (ROMCCR) and ROM corrective data register (ROMCDR). ROM Corrective Control Register
ROMCCR (00FE0H) 7 6 5 4 3 CM3 Corrective mode setting (BANK3) Corrective mode setting (BANK2) Corrective mode setting (BANK1) Corrective mode setting (BANK0) 0: Program jump mode 1: Data replacement mode 2 CM2 1 CM1 0 CM0 (Initial value: **** 0000)
CM3 CM2 CM1 CM0
R/W
ROM Corrective Status Register
ROMCSR (00FE1H) 7 6 5 4 3 2 WDC 1 0 (Initial value: ***0 0000) Read only
WDC
Write data counter
Counting the number of the byte written in ROMCDR
ROM Corrective Data Register
ROMCDR (00FE2H) 7 6 5 4 3 2 1 0 (Initial value: 0000 0000) Write only
ROMC
ROM Corrective data register
Figure 1.7.2 ROM Corrective Control Register, Status Register and ROM Corrective Data Register (1) Enable and disable The ROM corrective function is disabled after releasing reset. It is enabled after setting the data for one bank into ROMCDR. And the address-trap-reset is not generated when fetching an instruction from the RAM area except the address 02C0H to 06BFH. After the ROM corrective function is enabled, it is neccesary to reset the micro controller in order to disable it. (2) Data replacement mode The ROM corrective function has the program jump mode and the data replacement mode. By setting CMx (x: 0 to 3) in ROMCCR, the data replacement mode is selected. (3) The ROM corrective data register writing The ROM corrective data register has four banks corresponding to four independent locations to patch. The write data counter (WDC) points each bank set. (Figure 1.7.2)
88CS34-37
2003-03-25
TMP88CS34/CP34
ROM Corrective Data Register
ROMCDR (Initial value: 0000 0000) (00FE2H) ROMC7 ROMC6 ROMC5 ROMC4 ROMC3 ROMC2 ROMC1 ROMC0 The value of WDC after writing a data to ROMCDR 00000 (Initial value) The lower start address of the corrective area (8 bits) The middle start address of the corrective area (8 bits) BANK 0 The upper start address of the corrective area (4 bits) The lower 8 bit of the jump address/replacement data The middle 8 bit of the jump address/replacement data The upper 4 bit of the jump address/replacement data The lower start address of the corrective area (8 bits) The middle start address of the corrective area (8 bits) BANK 1 The upper start address of the corrective area (4 bits) The lower 8 bit of the jump address/replacement data The middle 8 bit of the jump address/replacement data The upper 4 bit of the jump address/replacement data The lower start address of the corrective area (8 bits) The middle start address of the corrective area (8 bits) BANK 2 The upper start address of the corrective area (4 bits) The lower 8 bit of the jump address/replacement data The middle 8 bit of the jump address/replacement data The upper 4 bit of the jump address/replacement data The lower start address of the corrective area (8 bits) The middle start address of the corrective area (8 bits) BANK 3 The upper start address of the corrective area (4 bits) The lower 8 bit of the jump address/replacement data The middle 8 bit of the jump address/replacement data The upper 4 bit of the jump address/replacement data Note 1: Note 2: WDC value equals to the number of the byte stored in ROMCDR. ROMCDR is set in order of the lower (8 bits), the middle (8 bits) and the upper (4 bits) start address of the corrective area, the lower (8 bits), the middle (8 bits) and the upper (4 bits) of the jump address/the replacement data. 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 00000
Figure 1.7.3 Banks and WDC Value of the Program Corrective Data Register Whenever ROMCDR is written, WDC is incremented to indicate what data is writen via ROMCDR. During reset, WDC is intialized to "0". (1) The lower start address of the corrective area (8 bits) (2) The middle start address of the corrective area (8 bits) (3) The upper start address of the corrective area (4 bits) (4) The lower jump address/replacement data (8 bits) (5) The middle jump address/replacement data (8 bits) (6) The upper jump address (4 bits)/replacement data Note 1: Corrective addresses must have over five addresses each other. Note 2: The address of an instruction for IDLE mode cannot be specificated as start address of corrective area.
88CS34-38
2003-03-25
TMP88CS34/CP34 1.7.3 Functions
The ROM corrective function can correct maximum four ROM areas with their corresponding four banks of ROM corrective registers. Either program jump mode or data replacement mode is selected for each bank by CM0 to CM3 respectively. (1) Program jump mode In the program jump mode, the system executes a jump instruction when the program execution reaches the instruction at the corrective ROM address, skips from the instruction which would have been executed, and executes an instruction at a preset jump address. Clearing ROMCCR CMx (x: 0 to 3) to "0" puts the system in the program jump mode. Use ROMCDR to set the corrective ROM address and jump address. When the start address of an erroneous program is a corrective ROM address, and that of the patch program is a jump address, the bug in the erroneous program can be fixed. Note that the patch program should end with a jump instruction, which causes a return to the built-in ROM. Note: For program jump mode, the address to be corrected must be the start address of the instruction.
Example 1: Setting the Program Correction Circuit with the Initial Routine Using the initial routine program, which is executed right after reset, set the program correction circuit's register and stores the patch program into the built-in RAM as follows. 1. 2. 3. 4. 5. 6. 7. 8. Read the flag, which indicates whether to use the program correction circuit, from the external memory. If that circuit is not used, perform normal initial processing. If it is used, clear CMx to 0 to establish the program jump mode. Read the corrective ROM address and jump address from the external memory. Set the corrective ROM address and jump address, which were read in step 4., in ROMCDR. Read the number of bytes for the patch program from the external memory. Read the program with a number of bytes, equal to the byte count read in step 6., from the external memory, and store that program into the built-in RAM. Repeat steps 4. through 7. as many times as there are required banks.
Example 2: There is bugs on the locations from 0C020H to 0C085H The corrective address, the jump vector, the program patch codes and other information to patch the ROM with the bugs must be read out from any of memory storage that holds them during initial program routine. CMn 0 specifies the program jump mode. Subsequently, the patch program codes are loaded into RAM (00400H to 004EFH). The start address (0C020H) of the ROM necessary to patch is written to the corrective ROM address registers, and the start address (00400H) of the RAM area to patch is loaded onto the jump address registers. When the instruction at 0C020H is fetched, the instruction to jump into 00400H is unconditionally executed instead of the instruction at 0C020H, and the subsequent patch program codes are executed. The jump instruction at the end of the patch program codes returns to the ROM at 0C086H.
88CS34-39
2003-03-25
TMP88CS34/CP34
00000H SFR 0003FH 00040H 006BFH JP 0C086H 00F80H DBR 00FFFH 04000H ROM 0C020H 0C085H 0C086H Bug area Return 004EFH 004F0H 00400H RAM Patch program
FFFFFH
Note:
Corrective address must be assigned to 1st byte of instruction codes on the program jump mode.
(2) Data replacement mode In the data replacement mode, the system replaces reference data stored in the ROM area with the new instead of correcting the data reference instruction when that reference data is changed. The program jump mode reduces the complexity of correcting the processing routine. However, when this mode is used, if there is a need to replace only the fixed data in ROM, the instruction to reference this ROM data should be corrected. Thus, a large amount of ROM is required for the patch program. To avoid this, the system has the data replacement mode. With this mode, three consecutive bytes of data can be replaced for each bank. (For an instruction which accesses only one byte, only the first byte can be replaced. For an instruction which accesses only two bytes, the two consecutive bytes can be replaced.) Setting ROMCCR CMx (x: 0 to 3) to "1" puts the system in the data replacement mode. Specify the start address of ROM data to be replaced as the corrective ROM address. Then, specify the new three-byte data as the patch data. Note: For data replacement mode, the corrective address should be the address of fixed data (including a vector). (The operation code and operand cannot be changed.)
Example 1: Setting the Program Correction Circuit with the Initial Routine Using the initial routine program, which is executed right after reset, set the program correction circuit's register as follows. 1. 2. 3. 4. 5. 6. Read the flag, which indicates whether to use the program correction circuit, from the external memory. If that circuit is not used, perform normal initial processing. If it is used, set CMx to "1" to establish the data replacement mode. Read the address of the data to be replaced and the patch data from the external memory. Set the address and patch data, which were read in step 4., in ROMCDR. Repeat steps 4. and 5. as many times as there are required banks.
88CS34-40
2003-03-25
TMP88CS34/CP34
Example 2: Replacing data 55H at 0C020H with 33H Using the initial routine program, which is executed right after reset, read the start address of the data to be replaced and the patch data from the external memory. Set CMx (x: 0 to 3) to "1" to change the correction mode to the data replacement mode. Specify the start address (0C020H) of the data to be replaced as the corrective ROM address. Then, specify the new three-byte data (33H for 0C020H, CCH for 0C021H, and C3H for 0C022H) as the patch data.
00000H SFR 0003FH 00040H RAM 006BFH
00F80H DBR 00FFFH 04000H ROM 0C020H 0C021H 0C022H 55H AAH A5H 33H CCH 3CH replacement data
FFFFFH 1. 2. 3. 4. At HL At HL At HL At HL 0C020H, Executing LD A, (HL) loads 33H in A. (Data replacement) 0C021H, Executing LD A, (HL) loads AAH in A. (No data replacement) 0C020H, Executing LD WA, (HL) loads CC33H in WA. (Data replacement) 0C020H, Executing LD IX, (HL) loads CCC33H in IX. (Data replacement)
Note 1: Corrective address must be assigned to constant data area on the data replacement mode. (Ope-code and Ope-rand cannot be replaced by ROM correction circuit.) Note 2: Instructions which includes "(HL )" or "( HL) " operation cannot be replaced by ROM corrective circuit on the data replacement mode.
88CS34-41
2003-03-25
TMP88CS34/CP34
2.
2.1
On-Chip Peripheral Functions
Special Function Registers (SFR) and Data Buffer Registers (DBR)
The TLCS-870/X series uses the memory mapped I/O system and all peripheral control and data transfers are performed through the special function registers (SFR) and data buffer registers (DBR). The SFR are mapped to addresses 00000H to 0003FH, and DBR are mapped to address 00F80H to 00FFFH. Figure 2.1.1 shows the list of the TMP88CS34/CP34 SFRs and-DBRs.
Address 00000H 00001 00002 00003 00004 00005 00006 00007 00008 00009 0000A 0000B 0000C 0000D 0000E 0000F 00010 00011 00012 00013 00014 00015 00016 00017 00018 00019 0001A 0001B 0001C 0001D 0001E 0001F Read
Reserved Reserved P2 port P3 port P4 port P5 port P6 port P7 port P5CR1 (P5 port I/O control1) P7CR (P7 port I/O control) Reserved Reserved P4CR (P4 port I/O control) P6CR (P6 port I/O control) ADCCRA (AD converter control A) ADCCRB (AD converter control B) TC1DRAL TC1DRAH TC1DRBL TC1DRBH TC1CR (TC1 control) TC2CR (TC2 control) TC2DRL TC2DRH TC3DRA (Timer register 3A) TC3DRB (Timer register 3B) TC3CR (TC3 control) TC4DR (Timer register 4) TC4CR (TC4 control) ORDSN (OSD control) ORCRAL (OSD control) ORCRAH (OSD control) (Timer register 2) (Timer register 1B) (Timer register 1A)
Write
Address 00020H 00021 00022 00023 00024 00025 00026 00027 00028 00029 0002A 0002B 0002C 0002D 0002E 0002F 00030 00031 00032 00033 00034 00035 00036 00037 00038 00039 0003A 0003B 0003C 0003D 0003E 0003F
Read
SBISRA (SBI status A)
Write
SBICRA (SBI control register A) I2CAR (I2C Bus address) SBIDBR (SBI Data buffer)
SBISRB (SBI status B)
SBICRB (SBI control register B) ORDMAL (OSD control) ORDMAH (OSD control)
RCSR (TC3 status)
RCCR (TC3 control) PMPXCR (Port control) PWMCR1A (PWM control1A) PWMCR1B (PWM control1B) PWMDBR1 (PWMDBR1) P3CR1 (P3 I/O control)
EIRE EIRD ILE ILD
(Interrupt enable register) (Interrupt latch)
CGCR (Divider control) ADCDR1 (AD conversion result) ADCDR2 (AD conversion result) Reserved WDTCR1 WDTCR2 TBTCR (TBT/TG control) EINTCR (External interrupt control) SYSCR1 SYSCR2 EIRL EIRH ILL ILH PSWL PSWH (Program status word) (Interrupt latch) (Interrupt enable register) (System control) Watch-dog timer control
(a) Special function registers Note 1: Note 2: Note 3: Do not access reserved areas by the program. : Cannot be accessed. Write-only registers and interrupt latches cannot use the read-modify-write instructions (bit manipulation instructions such as SET, CLR, etc. and logical operation instructions such as AND, OR, etc.). Note 4: When defining address 0003FH with assembler symbols, use GRBS. Address 0003EH must be GPSW/GFLAG.
Figure 2.1.1 (a) SFR
88CS34-42
2003-03-25
TMP88CS34/CP34
Address 00F80H 81H B9H CEH CFH D0H D1H E0H E1H E2H E3H E4H E5H E6H E7H E8H E9H EAH EBH ECH EDH EEH EFH F0H F1H F2H FEH FFH
Read
ORDON (OSD Control)
Write
OSD Control Register OSD Control Register
ORIRC (OSD Display Counter)
ORIRC (OSD Interrupt Control) OSD Control Register OSD Control Register Reserved
IDLEINV (Key-on Wake-up Status)
IDLECR (Key-on Wake-up Control) Reserved Reserved
ROMCCR (ROM Corrective Control) ROMCC (Data Register Count) ROMCDR (ROM Corrective Data) Reserved JECR (Jitter Elimination Control) JESR (Jitter Elimination Status) Reserved Reserved RXCR1 (Remote Control Receive Control) RXCR2 (Remote Control Receive Control) RXCTR (Remote Control Receive Counter) RXDBR (Remote Control Receive Data) RXSR (Remote Control Receive Status) Reserved FC8CR (Frequency Division Circuit Control) Reserved SCCRA (Baud Rate Control A) SCCRB (Baud Rate Control B) SCSR (Baud Rate Status) Reserved Reserved PSELCR (Port3 and 5 Output Status Control) DGINE (Input Control)
(b) Data buffer register Note 1: Note 2: Note 3: Do not access reserved areas by the program. : Cannot be accessed. Write-only registers cannot use the read-modify-write instructions (bit manipulation instructions such as SET, CLR, etc. and logical operation instructions such as AND, OR, etc.).
Figure 2.1.1 (b) DBR
88CS34-43
2003-03-25
TMP88CS34/CP34
2.2
I/O Ports
The TMP88CS34/CP34 has 6 parallel input/output ports (33 pins) as follows: Primary Function
Port P2 Port P3 Port P4 Port P5 1-bit I/O port 6-bit I/O port 8-bit I/O port 8-bit I/O port
Secondary Functions
External interrupt input, and STOP mode release signal input External interrupt input, remote control signal input, data slicer analog input, timer/counter input, serial bus interface input/output Pulse width modulation output External interrupt input, timer/counter input, key-on wake-up input, serial bus interface input/output, analog input and I output from OSD circuitry. R, G, B and Y/BL output from OSD circuitry, R.G.B and Y/BL input, analog input, and key-on wake-up input Horizontal synchronous pulse input and vertical synchronous pulse input to OSD circuitry
Port P6 Port P7
8-bit I/O port 2-bit I/O port
Each output port contains a latch, which holds the output data. All input ports do not have latches, so the external input data should either be held externally until read or reading should be performed several times before processing. Figure 2.2.1 shows input/output timing examples. External data is read from an I/O port in the S1 state of the read cycle during execution of the read instruction. This timing can not be recognized from outside, so that transient input such as chattering must be processed by the program. Output data changes in the S2 state of the write cycle during execution of the instruction which writes to an I/O port.
Fetch cycle Instruction execution cycle Input strobe Fetch cycle Read cycle
S0 S1 S2 S3 S0 S1 S2 S3 S0 S1 S2 S3 Ex: LD A, (x)
Data input (a) Input timing Fetch cycle Instruction execution cycle Output latch pulse Data output (b) Output timing NOTE: The positions of the read and write cycles may vary, dispending on the instruction. Fetch cycle Write cycle
S0 S1 S2 S3 S0 S1 S2 S3 S0 S1 S2 S3 Ex: LD (x), A
Figure 2.2.1 Input/Output Timing (Example)
88CS34-44
2003-03-25
TMP88CS34/CP34
When reading an I/O port except programmable I/O ports, whether the pin input data or the output latch contents are read depends on the instructions, as shown below: (1) Instructions that read the output latch contents 1. 2. 3. 4. 5. 6. 7. XCH r, (src) SET/CLR/CPL (src).b SET/CLR/CPL (pp).g LD (src).b, CF LD (pp).b, CF ADD/ADDC/SUB/SUBB/AND/OR/XOR (src), n (src) side of ADD/ADDC/SUB/SUBB/AND/OR/XOR (src), (HL)
(2) Instructions that read the pin input data 1. 2. Instructions other than the above (1) (HL) side of ADD/ADDC/SUB/SUBB/AND/OR/XOR (src), (HL)
2.2.1
Port P2 (P20)
Port P2 is a 1bit input/output port. It is also used as an external interrupt input, and a STOP mode release signal input. When used as an input port, or a secondary function pin, the output latch should be set to "1". During reset, the output latch is initialized to "1". It is recommended that pin P20 should be used as an external interrupt input, a STOP mode release signal input, or an input port. If used as an output port, the interrupt latch is set on the falling edge of the P20 output pulse. When a read instruction for port P2 is executed, bits 7 to 1 in P2 are read in as undefined data.
SET/CLR/CPL/others
Output latch Data input Data input Control input STOP OUTEN D Q P20 ( INT5 / STOP )
7 P2 (00002H) Note:
6
5
4
3
2
1
0 P20
INT5 STOP
(Initial value: **** ***1)
*: Don't care
Figure 2.2.2 Port P2
88CS34-45
2003-03-25
TMP88CS34/CP34 2.2.2 Port P3 (P35 to P30)
Port P3 is an 6-bit input/output port which can be configured as an input or an output in one-bit unit under software control. Input/output mode is specified by the corresponding bit in the port P3 input/output control register 1 (P3CR1). Port P3 is configured as an input if its corresponding P3CR1 bit is cleared to "0", and as an output if its corresponding P3CR1 bit is set to "1". During reset, P3CR1 is initialized to "0", which configures port P3 as an input. The P3 output latches are also initialized to "1". Data is written into the output latch regardless of the P3CR1 contents. Therefore initial output data should be written into the output latch before setting P3CR1. Port P3 is also used as an external interrupt input, Remote-control signal input a timer/counter input, and serial bus interface input/output. When used as a secondary function input pin except I2C bus interface input/output, the input pins should be set to the input mode. When used as a secondary function output pin except I2C bus interface input/output, the output pins should be set to the output mode and beforehand the output latch should be set to "1". When P34 and P35 are used as I2C bus interface input/output, P3CR2 bits should be set to the sink open drain mode, the output latches should be set to "1", and the output pins should be set to the output mode. Note: Input mode port is read the state of input pin. When input/output mode is used mixed, the contents of output latch setting input mode may be changed by executing bit manipulation instructions. 5AH
Example 1: Outputs an immediate data 5AH to port P3 (P3), 5AH ; P3 LD
Example 2: Inverts the output of the lower 4 bits (P33 to P30) in port P3 P33 to P30 (P3), 00001111B ; P33 to P30 XOR
88CS34-46
2003-03-25
TMP88CS34/CP34
STOP OUTEN P3jCR1 Data input Control input P3iCR2
STOP OUTEN P3jCR1 Data input Control input (*1)
Data output Control output
D
Q P3i
Data output VIN (*2)
D
Q P3j
Output latch (a) P35 to P34 7 P3 (00003H) 6 5 P35 SDA0 4 P34 SCL0 3 P33 TC4
Output latch (b) P33 to P30
2 P32
1 P31 INT4 TC3 1
0 P30 INT3 RXIN 0
(Initial value: **11 1111)
P3CR1 (0002BH)
7
6
5
4
3
2
P35CR1 P34CR1 P33CR1 P32CR1 P31CR1 P30CR1 P3CR1 I/O Control for P3 0: Input mode 1: Output mode 4 3 "0" 2 1 0 "0"
(Initial value: **00 0000) Write only
PSELCR (0FFEH)
7 "0" P3CR2
6 "0"
5
P35CR2 P34CR2 I/O Control for P3
P52CR2 P51CR2 0: Sink open drain 1: Tri-state
(Initial value: 0*00 *00*) Write only
(*1) only P33, P31, P30 (*2) only P33, P32 Note 1: Note 2: *: Don't care, i 5 to 4, j 3 to 0
P3CR1 cannot used the read-modify-write instructions. (Bit manipulation instructions such as SET, CLR, etc. and logical operation such as AND, OR, etc.)
Note 3:
Clear bit 7, 6, 3 and 0 to "0" in PSELCR.
Figure 2.2.3 Port P3 and P3CR
88CS34-47
2003-03-25
TMP88CS34/CP34 2.2.3 Port P4 (P47 to P40)
Port P4 is an 8-bit input/output port which can be configured as an input or an output in one-bit unit under software control. Input/Output mode is specified by the corresponding bit in the port P4 input/output control register (P4CR). Port P4 is configured as an input if its corresponding P4CR bit is cleared to "0", and as an output if its corresponding P4CR bit is set to "1". During reset, P4CR is initialized to "0", which configures port P4 as an input. The P4 output latches are also initialized to "1". Data is written into the output latch regardless of the P4CR contents. Therefore initial output data should be written into the output latch before setting P4CR. Port P4 is also used as a pulse width modulation (PWM) output. When used as a PWM output pin, the output pins should be set to the output mode and beforehand the output latch should be set to "1". Note: Input mode port is read the state of input pin. When input/output mode is used mixed, the contents of output latch setting input mode may be changed by executing bit manipulation instructions.
STOP OUTEN P4iCR Data input
Data output
PWMj
DQ Output latch P4i
7 P4 (00004H) P4CR (0000CH) P47
6 P46
5 P45
4 P44
3 P43
PWM3
2 P42
PWM2
1 P41
PWM1
0 P40
PWM0
(Initial value: 1111 1111)
7 P47CR
6 P46CR
5 P45CR
4 P44CR
3 P43CR
2 P42CR
1 P41CR
0 P40CR (Initial value: 0000 0000) Write only
P4CR Note 1: Note 2: Note 3: i j
I/O Control for port P4 7 to 0 3 to 0
0: Input mode 1: Output mode
P4CR cannot be used with the read-modify-write instructions. (Bit manipulation instructions such as SET, CLR, etc. and logical operation such as AND, OR, etc.)
Figure 2.2.4 Ports P4 and P4CR
88CS34-48
2003-03-25
TMP88CS34/CP34 2.2.4 Port P5 (P57 to P50)
Port P5 is an 8-bit input/output port which can be configured as an input or an output in one-bit unit under software control. Input/output mode is specified by the corresponding bit in the port P5 input/output control register 1 (P5CR1). Port P5 is configured as an input if its corresponding P5CR1 bit is cleared to "0", and as an output if its corresponding P5CR1 bit is set to "1". During reset, P5CR1 is initialized to "0", which configures port P5 as an input. The P5 output latches are also initialized to "1". Data is written into the output latch regardless of the P5CR1 contents. Therefore initial output data should be written into the output latch before setting P5CR1. Port P5 is also used as is also used as AD converter analog input, external interrupt input, timer/counter input, serial bus interface input/output, and an on screen display (OSD) output (I signal). When used as a secondary function input pin except I2C bus interface input/output, the input pins should be set to the input mode. When used as a secondary function output pin except I2C bus interface input/output, the output pins should be set to the output mode and beforehand the output latch should be set to "1". When P52 and P51 are used as I2C bus interface input/output, P5CR2 bits should be set to the sink open drain mode, the output latches should be set to "1", and the output pins should be set to the output mode. When P57 is used as an OSD output pin, the output pin should be set to the output mode and beforehand the port 6 data selection register (PIDS) should be clear to "0". When used as port P5, the port 6 data selection register (PIDS) should be set to "1". Note: Input mode port is read the state of input pin. When input/output mode is used mixed, the contents of output latch setting input mode may be changed by executing bit manipulation instructions.
88CS34-49
2003-03-25
TMP88CS34/CP34
STOP OUTEN P5iCR1 Data input
DGINEx Analog input AINDS SAIN STOP OUTEN P5jCR1 Data input D Q BY A S
Data output I PIDS
Output latch
P5i
Data output
D
Q P5j
(a) P57 DGINEx Analog input AINDS SAIN STOP OUTEN P5kCR1 Data input Control input Data output Control output (c) P53 STOP OUTEN P5mCR1 Data input Control input Data output D Q P5m D Q P5k Data output Control output STOP OUTEN P5lCR1 Data input Control input P5lCR2
Output latch (b) P56 to P54
D
Q P5l
Output latch
Output latch
(d) P52 to P51
Output latch Control output (e) P50 7 P57 I 6 P56 AIN3 5 P55 AIN2 4 P54 AIN1
P5 (00005H)
3 P53 INT2 TC1
SCK1
2 P52 SO1 SDA1
1 P51 SL1 SCL1
0 P50 INT0 TC2
(Initial value: 1111 1111)
AIN0 P5CR1 (00008H) 7 6 5 4 3 2 1 0 (Initial value: 0000 0000) Write only 1 0 (Initial value: 0*00 *00*) Write only
P57CR1 P56CR1 P55CR1 P54CR1 P53CR1 P52CR1 P51CR1 P50CR1 P5CR1 I/O Control for P5 0: Input mode 1: Output mode 4 3 "0" 2
PSELCR (00FFEH)
7 "0"
6 "0"
5
P35CR2 P34CR2
P52CR2 P51CR2
P5CR2
I/O Control for P5
0: Sink open drain 1: Tri-state
Figure 2.2.5 Ports P5 (1/2)
88CS34-50
2003-03-25
TMP88CS34/CP34
ORP6S (00FBAH)
7 P67S
6 P66S
5 P65S
4 P64S
3 PIDS
2 YBLCS
1 MPXS
0 (Initial value: 0000 0000) Write only 0 (Initial value: **11 1111)
PIDS
Selection of the output data for port P57 6 5 4
0: The OSD output (I) 1: Port P57 output latch 3 2 1
DGINE (00FFFH)
7
DGINE5 DGINE4 DGINE3 DGINE2 DGINE1 DGINE0
DGINE0 DGINE1 Input control register DGINE2 DGINE3 Note 1: Note 2: *: Don't care, i 7, j 6 to 4, k 3, l
0: P53 port input/TC1 input/S10 input/INT2 input disable 1: P53 port input/TC1 Input/S10 input/INT2 input enable 0: P54 port input disable 1: P54 port input enable 0: P55 port input disable 1: P55 port input enable 0: P56 port input disable 1: P56 port input enable 2 to 1, m 0
Write only
P5CR1 cannot be used with the read-modify-write instructions. (Bit manipulation instructions such as SET, CLR, etc. and logical operation such as AND, OR, etc.)
Note 3:
Clear bit 7, 6 and 3 to "0" in PSELCR.
Figure 2.2.6 Ports P5 (2/2)
2.2.5
Port P6 (P67 to P60)
Port P6 is an 8-bit input/output port which can be configured as an input or an output in one-bit unit under software control. Input/output mode is selected by the corresponding bit in the port P6 input/output control register (P6CR). Port P6 is configured as an input if its corresponding P6CR bit is cleared to "0", and as an output if its corresponding P6CR bit is set to "1" and P6nS bit is set to "1". P63 to P60 are sink open drain ports. During reset, P6CR is initialized to "0", which configures port P6 as an input. The P6 output latches are also initialized to "1". Data is written into the output latch regardless of the P6CR contents. Therefore initial output data should be written into the output latch before setting P6CR. Port P6 is used as an on screen display (OSD) output (R, G, B, and Y/BL signal)/input (RIN, GIN BIN, Y/BLIN signal), a test video signal output and AD converter analog input. When used as a secondary function input, the input pins should be set to the input mode. When used as an OSD output pin, the output pins should be set to the output mode and beforehand the port P6 data selection register (P67S to P64S) should be clear to "0". When used as port P6, the signal control register (P67 to P64) should be set to "1". Note1: Input mode port is read the state of input pin. When input/output mode is used mixed, the contents of output latch setting input mode may be changed by executing bit manipulation instructions. Note2: P63 to P61 output "0" after a reset. When these dual-function pins are used as ports, be sure to set ORP6S2 to "1" Example: Sets the lower 4 bits (P63 to P60) in port P6 to the output mode, and the other bit to the input mode. LD (P6CR), 0FH ; P6CR 00001111B
88CS34-51
2003-03-25
TMP88CS34/CP34
STOP OUTEN P6iCR Data input
STOP OUTEN P6jCR Data input RIN, GIN
Data output R, G, B, Y/BL P6iS
D
Q
AY BS P6i Data output D Q P6j Output latch (a) P67 to P64 (b) P63 to P62
Output latch
DGINEx Analog input AINDS SAIN STOP OUTEN P6kCR Data input BIN, Y/BLIN Data output
D
Q P6k
Output latch (c) P61 to P60 P6 (00006H) 7 P67 Y/BL 6 P66 B 5 P65 G 4 P64 R 3 P63 RIN
2 P62 GIN
1 P61 BIN AIN5 1 P61CR
0 P60 Y/BLIN AIN4 0 P60CR
(Initial value: 1111 1111)
P6CR (0000DH)
7 P67CR P6CR
6 P66CR
5 P65CR
4 P64CR
3 P63CR
2 P62CR
(Initial value: 0000 0000) Write only
I/O Control for port P6
0: Input mode 1: Output mode 3 PIDS 2 YBLCS 1 MPXS 0
ORP6S (00FBAH)
7 P67S
6 P66S
5 P65S
4 P64S
(Initial value: 0000 0000) Write only
P67S to P64S
Selection of the output data for port P6i 5 4 3
0: The OSD output (R, G, B, Y/BL) 1: Port P6i output latch 2 1 0
DGINE (00FFFH)
7
6
DGINE5 DGINE4 DGINE3 DGINE2 DGINE1 DGINE0 0: 1: 0: 1: 3 P60 port input/YIN/BLIN disable P60 port input/YIN/BLIN enable P61 port input/BIN disable P61 port input/BIN enable 2 1 0
(Initial value: **11 1111)
DGINE4 Input Control register DGINE5 ORP6S2 (00FA1H) 7 6 5 4
Write only
Fixed at 1 Fixed at 1 Fixed at 1
(Initial value: **** 000*) Write only
Be sure to fix these bits to "1", using the initial routine. Note 1: Note 2: Note3: *: Don't care, i 7 to 4, j 1 to 0
P6CR and ORP6S cannot be used with the read-modify-write instructions. (Bit manipulations such as SET, CLR, etc. and logical operation such as AND, OR, etc.) P63 to P61 output "0" after a reset. When these dual-function pins are used as port, be sure to set ORP6S2 to "1".
Figure 2.2.7 Ports P6, P6CR, and P67S to P64S
88CS34-52
2003-03-25
TMP88CS34/CP34 2.2.6 Port P7 (P71 to P70)
Port P7 is a 2bit input/output port, and is also used as a vertical synchronous signal ( VD ) input and a horizontal synchronous signal ( HD ) input for the on screen display (OSD) circuitry. The output latches, are initialized to "1" during reset. When used as an input port or a secondary function pin, the output latch should be set to "1". When a read instruction for port P7 is executed, bits 7 to 2 in P7 are read in as undefined data.
STOP OUTEN P7iCR Data input
HD , VD
Data output
D
Q P7i
Output latch 7 P7 (00007H) P7CR (00009H) 7 6 5 4 3 2 6 5 4 3 2 1 P71
VD
0 P70
HD
(Initial value: **** **11)
1 P71CR
0 P70CR (Initial value: **** **00) Write only
P7CR Note 1: i
I/O Control for P7 1 to 0, *: Don't care
0: Input mode 1: Output mode
Figure 2.2.8 Ports P7
88CS34-53
2003-03-25
TMP88CS34/CP34
2.3
Time Base Timer (TBT)
The time base timer generates time base for key scanning, dynamic displaying, etc. It also provides a time base timer interrupt (INTTBT). The time base timer is controlled by a control register (TBTCR) shown in Figure 2.3.1. An INTTBT is generated on the first rising edge of source clock (the divider output of the timing generator) after the time base timer has been enabled. The divider is not cleared by the program; therefore, only the first interrupt may be generated ahead of the set interrupt period. The interrupt frequency (TBTCK) must be selected with the time base timer disabled (When the time base timer is changed from enabling to disabling, the interrupt frequency can't be changed.) Both frequency selection and enabling can be performed simultaneously.
TBTCK t1 t2 t1 t2 0 1 machine cycle
TBTEN
Example: Sets the time base timer frequency to fc/216 [Hz] and enables an INTTBT interrupt. LD (TBTCR) , 00001010B SET (EIRL). 6
fc/223, fc/224 fc/221, fc/222 fc/216, fc/217 fc/214, fc/215 fc/213, fc/214 fc/212, fc/213 fc/211, fc/212 fc/29, fc/210
MPX INTTBT interrupt A request B C Source clock Source clock Rising DY edge E detector F TBTEN G HS INTTBT 3 TBTCK TBTCR TBTEN Enable TBT Interrupt period
Time Base Timer Control Register (a) Configuration (b) Time Base Timer Interrupt
Figure 2.3.1 Time Base Timer
88CS34-54
2003-03-25
TMP88CS34/CP34
TBTCR (00036H)
7 "0"
6
5
4 "0"
3 TBTEN
2
1 TBTCK
0 (Initial value: 0**0 0***)
TBTEN
Time base timer enable/disable
0: Disable 1: Enable NORMAL, IDLE mode DV1CK 000 001 fc/221 fc/2 fc/2 fc/2 fc/2
16
0
DV1CK fc/222 fc/2
17
1 Write only
fc/223 [Hz]
fc/224 [Hz]
TBTCK
Time base timer interrupt frequency select
010 011 100 101 110 111
fc/214
13 12 11 9
fc/215 fc/214 fc/213 fc/212 fc/210
fc/2
Note 1: Note 2: Note 3:
fc: High-frequency clock [Hz], *: Don't care TBTCR is a write-only register and must not be used with any of read-modify-write instructions. Set bit 7 and 4 in TBTCR to "0".
Figure 2.3.2 Time Base Timer and Divider Output Control Register Table 2.3.1 Time Base Timer Interrupt Frequency (Example: at fc Time Base Timer Interrupt Frequency [Hz] TBTCK
000 001 010 011 100 101 110 111
16MHz)
NORMAL, IDLE mode DV1CK
1.90 7.62 244.14 976.56 1953.12 3906.25 7812.50 31250
0
DV1CK
0.95 3.81 122.07 488.28 976.56 1953.12 3906.25 15625
1
88CS34-55
2003-03-25
TMP88CS34/CP34
2.4
Watchdog Timer (WDT)
The watchdog timer is a fail-safe system to rapidly detect the CPU malfunctions such as endless looping caused by noise or the like, or deadlock and resume the CPU to the normal state. The watchdog timer signal for detecting malfunction can be selected either a reset output or a pseudo non-maskable interrupt request. However, selection is possible only once after reset. At first the reset output is selected. When the watchdog timer is not being used for malfunction detection, it can be used as a timer to generate an interrupt at fixed intervals.
2.4.1
Watchdog Timer Configuration
MPX Reset release signal from T.G. Binary Counters Y Clock 1 Clear Interrupt request 2 Overflow WDT output S
Q
fc/2 , fc/2 fc/221, fc/222 fc/219, fc/220 fc/217, fc/218
23
24
A B C DS 2
R Reset output
RESET
INTWDT
Internal reset Q S R
WDTT
WDTEN
Writing disable code Controller
Writing clear code
WDTOUT
00034H WDTCR1
00035H WDTCR2 MPX: Multiplexer
Watchdog timer control registers
Figure 2.4.1 Watchdog Timer Configuration
2.4.2
Watchdog Timer Control
Figure 2.4.2 shows the watchdog timer control registers (WDTCR1, WDTCR2). The watchdog timer is automatically enabled after reset. (1) Malfunction detection methods using the watchdog timer The CPU malfunction is detected at follows. 1. 2. Setting the detection time, selecting output, and clearing the binary counter. Repeatedly clearing the binary counter within the setting detection time. The watchdog timer consists of an internal divider and two-stage binary counter. Writing the clear code (4EH) clears the binary counter, but not the internal divider. The minimum overflow time for the binary counter might be three quarters of the WDTCR1 (WDTT) time setting depending on when the clear code (4EH) is written into the WDTCR2 register. So, write the clear code on a cycle which is shorter than that minimum overflow time.
Note:
88CS34-56
2003-03-25
TMP88CS34/CP34
If the CPU malfunctions such as endless looping or deadlock occur for any cause, the watchdog timer output will become active at the rising of an overflow from the binary counters unless the binary counters are cleared. At this time, when WDTOUT 1 a reset is generated, which drivers the RESET pin low to reset the internal hardware and the external circuit. When WDTOUT 0, a watchdog timer interrupt (INTWDT) is generated. The watchdog timer temporarily stops counting in STOP mode including warm-up or IDLE mode, and automatically restarts (continues counting) when the STOP/IDLE mode is released.
88CS34-57
2003-03-25
TMP88CS34/CP34
Example: Sets the watchdog timer detection time to 221/fc [s] and resets the CPU malfunction. LD (WDTCR2), 4EH ; Clears the binary counters LD LD Within 3/4 of WDT detection time LD Within 3/4 of WDT detection time LD
Watchdog Timer Register 1 7 WDTCR1 (00034H)
(WDTCR1), 00001101B ; (WDTCR2), 4EH ;
WDTT
10, WDTOUT
1
Clears the binary counters (always clear immediately before and after changing WDTT)
(WDTCR2), 4EH
;
Clears the binary counters
(WDTCR2), 4EH
;
Clears the binary counters
6
5
4
3 WDTEN
2 WDTT
1
0 WDTOUT
(Initial value: **** 1001)
WDTEN
Watchdog timer enable/disable
0: Disable (It is necessary to write the disable code to WDTCR2) 1: Enable NORMAL mode DV1CK 0 225 /fc 223/fc 221/fc 219/fc DV1CK 1 226/fc 224/fc 222/fc 220/fc
WDTT
Watchdog timer detection time [s]
00 01 10 11
Write only
WDTOUT Note 1: Note 2: Note 3: Note 4:
Watchdog timer output select
0: Interrupt request 1: Reset output
WDTOUT cannot be set to "1" by program after clearing WDTOUT to "0". fc: High-frequency clock [Hz], *: Don't care WDTCR1 is a write-only register and must not be used with any of read-modify-write instructions. The watchdog timer must be disabled or the counter must be cleared immediately before entering to the STOP mode. When the counter is cleared, the counter must be cleared again immediately after releasing the STOP mode.
Note 5:
Just right before disabling the watchdog timer, disable the acceptance of interrupts (DI) and clear the watchdog timer. If the watchdog timer is disabled under conditions other than the above, the proper operation cannot be guaranteed.
Watchdog Timer Register 2 7 WDTCR2 (00035H)
6
5
4
3
2
1
0 (Initial value: **** ****)
WDTCR2 Note 1: Note 2: Note 3: Note 4: Note 5:
Watchdog timer control code write register
4EH: Watchdog timer binary counter clear (clear code) B1H: Watchdog timer disable (disable code) Others: Invalid 0.
Write only
The disable code is invalid unless written when WDTEN *: Don't care
The binary counter of the watchdog timer must not be cleared by the interrupt task. Clears the binary counter does not clear the source clock. It is recommended that the time to clear is set to 3/4 of the detecting time. The watchdog timer counter must be disabled by writing the disable code (B1H) to WDRCR2 after writing WDTCR2 to. "4EH".
Figure 2.4.2 Watchdog Timer Control Registers
88CS34-58
2003-03-25
TMP88CS34/CP34
(2) Watchdog timer enable The watchdog timer is enabled by setting WDTEN (bit 3 in WDTCR1) to "1". WDTEN is initialized to "1" during reset, so the watchdog timer operates immediately after reset is released. Example: Disables watchdog timer LDW (WDTCR1), 00001000B (3) Watchdog timer disable To disable the watchdog timer, clear the interrupt mask enable flag (IMF) to "0" and write the clear code (4EH) into WDTCR2. Then, clear WDTEN (bit 3 in WDTCR1) to "0". When WDTEN is "0", the watchdog timer is disabled by writing the disable code (B1H) into WDTCR2. If WDTEN is cleared to "0" after the disable code has been written into WDTCR2, the watchdog timer is not disabled. While it is disabled, its binary counter is cleared. Example: DI LD LDW EI (WDTCR2), 4EH (WDTCR1), B101H ; ; ; ; Disables interrupt acceptance. Clears the watchdog timer. Disables the watchdog timer. Enables interrupt acceptance. ; WDTEN 1
Table 2.4.1 Watchdog Timer Detection Time (Example: fc = 16 MHz) Watchdog timer detection time [s] WDTT
00 01 10 11
NORMAL mode DV1CK = 0
2.097 524.288 m 131.072 m 32.768 m
DV1CK = 1
4.194 1.048 262.1 m 65.5 m
2.4.3
Watchdog Timer Interrupt (INTWDT)
This is a pseudo non-maskable interrupt which can be accepted regardless of the contents of the EIR. If a watchdog timer interrupt or a software interrupt is already accepted, however, the new watchdog timer interrupt waits until the previous interrupt processing is completed (the end of the [RETN] instruction execution). The stack pointer (SP) should be initialized before using the watchdog timer output as an interrupt source with WDTOUT. Example: Watchdog timer interrupt setting up LD SP, 023FH ; LD (WDTCR1), 00001000B ; Sets the stack pointer WDTOUT 0
2.4.4
Watchdog Timer Reset
If the watchdog timer output becomes active, a reset is generated, which drivers the
RESET pin (sink open drain input/output with pull-up) low to reset the internal hardware.
The reset output time is about 8/fc to 24/fc [s] (0.5 to 1.5 s at fc Note:
16.0 MHz).
If there is any fluctuation in the oscillation frequency at the start of clock oscillation, the reset time includes error. Thus, regard the reset time as an approximate value.
88CS34-59
2003-03-25
TMP88CS34/CP34
219/fc [s] 217/fc Clock Binary counter 1 2 3 0 1 2 3 0 (WDTT 11B)
Overflow INTWDT interrupt WDT reset output Writes 4EH to WDTCR2 (High-Z)
("L" output)
Figure 2.4.3 Watchdog Timer Interrupt/Reset
88CS34-60
2003-03-25
2.5
Note: S Y B MPX
Command start Set Q
2.5.1
MCAP1
A TC1S 2 Decoder Ext. trigger Rising Edge detector METT1 Falling
Clear
INTTC1 interrupt
Configuration
16-Bit Timer/Counter1 (TC1A)
Pulse width measurement mode
Ext. trigger start
INT2ES SAY B MPX
MPX B
Clear Clock
MPX
Be sure to set the function of input/output pins correctly. For details, see the section on I/O port control registers.
Figure 2.5.1 Timer/Counter 1
88CS34-61
fc/211, fc/212 fc/27 or fc/28 fc/23 or fc/24 AY S 16-bit up-counter 2
Window mode
TC1 pin D A BY C S
Pulse width measurement mode Match CMP
Capture
TC1DRB TC1CK TC1CR Timer/counter 1 control register SCAP1
TC1DRA 16-bit timer registers 1A, 1B
TMP88CS34/CP34
CMP: Comparator MPX: Multiplexer
2003-03-25
TMP88CS34/CP34 2.5.2 Control
The timer/counter 1 is controlled by a timer/counter 1 control register (TC1CR) and two 16-bit timer registers (TC1DRA and TC1DRB).
TC1DRA (00010, 00011H) TC1DRB (00012, 00013H) 7 TC1CR (00014H) "0" 6
ACPAP1 MCAP1 METT1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TC1DRAH (00011H) TC1DRBH (00013H) 5 TC1S 4 3 2 1 0
TC1DRAL (00010H) Read/Write TC1DRBL (00012H) Read only Read/Write (Initial value: 0000 0000)
TC1CK
TC1M
TC1M
TC1 operating mode select
00: 01: 10: 11:
Timer/external trigger timer/event counter mode Window mode Pulse width measurement mode Reserved NORMAL, IDLE mode DV7CK DV1CK 0 0, DVCK 00 DV1CK fs/212 fc/28 fc/24 External clock (TC1 pin input)
Timer Extend Event Window Pulse PPG
1
TC1CK
TC1 source clock select [Hz]
00 01 10 11
fc/211 fc/27 fc/2
3
R/W
TC1S
TC1 start control
ACAP1 MCAP1 METT1
Auto capture control Pulse width measurement mode control External trigger timer mode control Note 1: Note 2:
00: Stop and counter clear 01: Command start 10: External trigger start at the rising edge 11: External trigger start at the falling edge 0: Auto-capture disable 1: Auto-capture enable 0: Double edge capture 0: Trigger start 1: Single edge capture 1: Trigger start and stop
fc: High-frequency clock [Hz] The timer register consists of two shift registers. A value set in the timer register is put in effect at the rising edge of the first source clock pulse that occurs after the upper data (TC1DRAH) are written. Therefore, the lower byte must be written before the upper byte (it is recommended that a 16-bit access instruction be used in writing). Writing only the lower data (TC1DRAL) does not put the setting of the timer register in effect.
Note 3: Note 4: Note 5:
Set the mode, source clock PPG control and timer F/F control when TC1 stops (TC1S Auto-capture can be used in only timer, event counter, and window modes. Values to be loaded to timer registers must satisfy the following condition. TC1DRA TC1DRB, TC1DRA 1
00).
Note 6: Note 7:
Always write "0" to TFF1 except PPG output mode. On entering STOP mode, the TC1 start control (TC1S) is cleared to "00" automatically. So, the timer stops. Once the STOP mode has been released, to start using the timer counter, set TC1S again.
Figure 2.5.2 Timer Registers and TC1 Control Register
88CS34-62
2003-03-25
TMP88CS34/CP34 2.5.3 Function
Timer/counter 1 has five operating modes: timer, external trigger timer, event counter, window, pulse width measurement. (1) Timer mode In this mode, counting up is performed using the internal clock. The contents of TC1DRA are compared with the contents of up-counter. If a match is found, an INTTC1 interrupt is generated, and the counter is cleared to "0". Counting up resumes after the counter is cleared. The current contents of up-counter can be transferred to TC1DRB by setting ACAP1 (bit 6 in TC1CR) to "1" (software capture function). (Auto-capture function) Table 2.5.1 Source Clock (internal clock) for Timer/Counter 1 (Example: at fc NORMAL, IDLE mode TC1CK DV1CK Resolution [ s]
00 01 10 128.0 8.0 0.5
16.0 MHz)
0 Maximum time setting [s]
8.39 0.524 32.77 m
DV1CK Resolution [ s]
256.0 16.0 1.0
1
Maximum time setting [s]
16.78 1.049 65.54 m
Example 1: Sets the timer mode with source clock fc/211 [Hz] and generates an interrupt 1 later (at fc 16 MHz) LDW (TC1DRA), 1E84H ; Sets the timer register (1 s 211/fc 1E84H) DI SET (EIRL). 4 ; Enable INTTC1 EI LD (TC1CR), 00000000B ; Selects the source clock and mode LD (TC1CR), 00010000B ; Starts TC1 Example 2: Auto-capture LD (TC1CR), 01010000B LD WA, (TC1DRB) ; ; ACAP1 1 (Capture) Reads the capture value
88CS34-63
2003-03-25
TMP88CS34/CP34
Count start Source clock Up-counter TC1DRA INTTC1 interrupt 0 ? n Match detect Counter clear 1 2 3 4 n 1n 0 1 2 3 4 5 6 7
(a) Timer mode
Source clock Up-counter TC1DRB ACAP1 (b) Auto-capture m ? 2 m 1 m 1 m m 1 m 1 2 m 2 n 1 n 1 n n1 Capture n n 1
Capture m m
Figure 2.5.3 Timer Mode Timing Chart (2) External trigger timer mode In this mode, counting up is started by an external trigger. This trigger is the edge of the TC1 pin input. Either the rising or falling edge can be selected with TC1S. Source clock is an internal clock. The contents of TC1DRA is compared with the contents of up-counter. If a match is found, an INTTC1 interrupt is generated, and the counter is cleared to "0" and halted. The counter is restarted by the selected edge of the TC1 pin input. When METT1 (bit 6 in TC1CR) is "1", inputting the edge to the reverse direction of the trigger edge to start counting clears the counter, and the counter is stopped. Inputting a constant pulse width can generate interrupts. When METT1 is "0", the reverse directive edge input is ignored. The TC1 pin input edge before a match detection is also ignored. The TC1 pin input has the noise rejection; therefore, pulses of 7/fc [s] or less are rejected as noise. A pulse width of 13/fc [s] or more is required for edge detection in NORMAL or IDLE mode. Example 1: Detects rising edge in TC1 pin input and generates an interrupt 100 s later. (at fc 16.0 MHz, DV1CK 1) LDW (TC1DRA), 0064H ; 100 s 24/fc 64H DI SET (EIRL). 4 ; INTTC1 interrupt enable EI LD (TC1CR), 00001000B ; Selects the source clock and mode LD (TC1CR), 00101000B ; TC1 external trigger start, METT1 0 Example 2: Generates an interrupt, inputting "L" level pulse (pulse width: 4 ms or more) to the TC1 pin. (at fc 16.0 MHz, DV1CK 1) LDW (TC1DRA), 00FAH ; 4 ms 28/fc FAH DI SET (EIRL). 4 ; INTTC1 interrupt enable EI LD (TC1CR), 00000100B ; Selects the source clock and mode LD (TC1CR), 01110100B ; TC1 external trigger start, METT1 1
88CS34-64
2003-03-25
TMP88CS34/CP34
Count start TC1 pin input Internal clock Up-counter TC1DRA INTTC1 interrupt (a) Trigger start (METT1 Count start TC1 pin input Internal clock Up-counter TC1DRA INTTC1 interrupt (b) Trigger start and Stop (METT1 0 1 n 2 3
m 1m
Count start TC1S 10 at the rising edge
0 n
1
2
3
4
n
1
n Counter clear
0
1
2
3
Match detect
0) TC1S 10 at the rising edge
Count clear
Count start
0
1
2
3
n1n
0
Match detect 1)
Counter clear
Note: m
n
Figure 2.5.4 External Trigger Timer Mode Timing Chart (3) Event counter mode In this mode, events are counted at the edge of the TC1 pin input and bit 4 or 5 in TC1CR. Either the rising or falling edge can be selected with the external trigger. The contents of TC1DRA are compared with the contents of up-counter. If a match is found, an INTTC1 interrupt is generated, and the counter is cleared. Match detect is executed on other edge of count-up. A match can not be detected and INTTC1 is not generated when the pulse is still in same state. Setting ACAP1 to "1" transfers the current contents of up-counter to TC1DRB (Auto-capture function).
Count start TC1 pin input Up-counter TC1DRA INTTC1 interrupt ?
0 1 2 n 1 n 0 1 2
TC1S 10 at the falling edge
n
Match detect Counter clear
Figure 2.5.5 Event Counter Mode Timing Chart
88CS34-65
2003-03-25
TMP88CS34/CP34
Table 2.5.2 Input Pulse Width for Timer/Counter 1 Minimum pulse width [s] NORMAL/IDLE
"H" width "L" width 23/fc 23/fc
(4) Window mode Counting up is performed on the rising edge of the pulse that is the logical AND-ed product of the TC1 pin input (window pulse) and an internal clock. The contents of TC1DRA are compared with the contents of up-counter. If a match is found, an INTTC1 interrupt is generated, and the counter is cleared. Positive or negative logic for the TC1 pin input can be selected with bit4 or 5 in TC1CR. It is necessary that the maximum applied frequency be such that the counter value can be analyzed by the program. That is; the frequency must be considerably slower than the selected internal clock.
Count start Command start TC1 pin input Internal clock Up-counter TC1DRA INTTC1interrupt (a) Positive logic (at TC1S Command start TC1 pin input Internal clock Up-counter TC1DRA INTTC1 interrupt (b) Negative logic (at TC1S 11) ? 9 Match detect Counter clear 0 1 2 3 4 5 6 7 8 90 1 Count start 10) Count stop Count start ? 7 Match detect Counter clear 0 1 2 3 4 5 6 70 1 2 3 Count stop Count start
Figure 2.5.6 Window Mode Timing Chart (5) Pulse width measurement mode In this mode, counting is started by the external trigger (set to external trigger start by TC1CR). The trigger can be selected either the rising or falling edge of the TC1 pin input. The source clock is used an internal clock. On the next falling (rising) edge, the counter contents are transferred to TC1DRB and an INTTC1 interrupt is generated. The counter is cleared when the single edge capture mode is set. When double edge capture is set, the counter continues and, at the next rising (falling) edge, the counter contents are again transferred to TC1DRB. If a falling (rising) edge capture value is required, it is necessary to read out TC1DRB contents until a rising (falling) edge is detected. Falling or rising edge is selected with the external trigger TC1S (bit4 or 5 in TC1CR), and single edge or double edge is selected with MCAP1 (bit 6 in TC1CR).
88CS34-66
2003-03-25
TMP88CS34/CP34
Note 1: Be sure to read the captured value from TC1DRB before the next trigger edge is detected. If fail to read it, it becomes undefined. It is recommended that a 16-bit access instruction be used to read from TC1DRB. Note 2: If either the falling or rising edge is used in capturing values, the counter stops at "1" after a value has been captured until the next edge is detected. So, the value captured next will become "1" larger than the value captured right after capturing starts. Example: Duty measurement (resolution fc/27 [Hz] DV1CK 0) CLR (INTTC1SW). 0 ; INTTC1 service switch initial setting: Clears Bit 0 of INTTC1SW. This bit is inverted by CPL instruction before INTTC1 is generated. LD (TC1CR), 00000110B ; Sets the TC1 mode and source clock DI SET (EIRL). 4 ; Enables INTTC1 EI LD (TC1CR), 00100110B ; Starts TC1 with an external trigger . . at MCAP1 0 . . . . PINTTC1: CPL (INTTC1SW). 0 ; Complements INTTC1 service switch JRS F, SINTTC1 LD WA, (TC1DRBL) ; Reads TC1DRB ("H" level pulse width) Lower address in TC1DRBL: TC1DRB LD (HPULSE), WA RETI SINTTC1: LD WA, (TC1DRBL) ; Reads TC1DRB (Period) LD (WIDTH), WA . . . RETI ; Duty calculation . . . VINTTC1: DW PINTTC1 ; Sets INTTC1
WIDTH HPULSE TC1 pin
INTTC1 INTTC1SW
88CS34-67
2003-03-25
Count start
Count start
Trigger
TC1 pin input
Internal clock
0
n 1 m
Up-counter Capture
n
1
2
3
4
n0
1
2
3
4
1m0
1
Capture
m
TC1DRB
INTTC1 interrupt (a) Single edge capture (MCAP1 1) [Application] High or low pulse width measurement
Figure 2.5.7 Pulse Width Measurement Mode Timing Chart
Count start Count start
0
n 1 n 1 n 2
88CS34-68
1 2 3 4 n
m 1m0
TC1 pin input
Internal clock
1 2 3
n' 1 n' n' 1 n' 2
Up-counter Capture
n
Capture
m
Capture
n'
TC1DRB
INTTC1 interrupt (b) Double edge capture (MCAP1 0) [Application] (1) Period/Frequency measurement (2) Duty measurement
TMP88CS34/CP34
2003-03-25
TMP88CS34/CP34
2.6
16-Bit Timer/Counter 2 (TC2A)
Configuration
Port (Note) TC2S H Window Clear 16-bit up-counter
2.6.1
TC2 pin
fc/223 or fc/224 fc/213 or fc/214 fc/28 or fc/29 fc/23 or fc/24
A B CY D
B Timer/ event counter Y Source A clock S
TC2M S 3 TC2CK TC2S TC2DR TC2CR TC2 control register Note:
CMP
INTTC2 interrupt
16-bit timer register 2
MPX: Multiplexer CMP: Comparator
Propagation of control input/output requires the correct I/O port setting. For details, see the section on I/O ports.
Figure 2.6.1 Timer/Counter 2 (TC2)
88CS34-69
2003-03-25
TMP88CS34/CP34 2.6.2 Control
The timer/counter 2 is controlled by a timer/counter 2 control register (TC2CR) and a 16-bit timer register 2 (TC2DR). Reset does not affect TC2DR.
TC2DR (00016, 00017H) TC2CR (00015H) TC2M 15 14 13 12 11 10 9 8 7 6 5 4 Read/Write 7 6 5 TC2S TC2 operating mode select 4 3 TC2CK 2 1 0 TC2M (Initial value: **00 00*0) 3 2 1 0
TC2DRH (00017H)
TC2DRL (00016H)
0: Timer/event counter mode 1: Window mode NORMAL1/2, IDLE1/2 mode DV1CK 000 001 fc/223 fc/213 fc/2 fc/2
8 3
0
DV1CK fc/224 fc/214 fc/29 fc/24
1
TC2CK
TC2 source clock select [Hz]
010 011 100 101 110 111
Write only
Reserved Reserved Reserved
Reserved Reserved
External clock (TC2 pin input)
TC2S
TC2 start control Note 1: Note 2:
0: Stop and counter clear 1: Start
fc: High-frequency clock [Hz], *: Don't care Writing to the lower byte of timer register 2 (TC2DRL), the comparison is inhibited until the upper byte (TC2DRH) is written. After writing to the upper byte, any match during 1 machine cycle (instruction execution cycle) is ignored.
Note 3: Note 4:
Set the mode and source clock when the TC2 stops (TC2S
0).
Values to be loaded to timer register must satisfy the following condition. TC2DR 1
Note 5: Note 6:
TC2CR are write-only registers and must not be used with any of the read-modify-write instructions. When STOP mode is started, timer counter is stopped and cleared. Set TC2S to "1" after STOP mode is released for restarting timer counter.
Figure 2.6.2 Timer Register 2 and TC2 Control Register
88CS34-70
2003-03-25
TMP88CS34/CP34 2.6.3 Function
The timer/counter 2 has three operating modes: timer, event counter and window modes. (1) Timer mode In this mode, the internal clock is used for counting up. The contents of TC2DR are compared with the contents of up-counter. If a match is found, a timer/counter 2 interrupt (INTTC2) is generated, and the counter is cleared. Counting up is resumed after the counter is cleared. Table 2.6.1 Source Clock (internal clock) for Timer/Counter 2 (at fc NORMAL, IDLE mode TC2CK DV1CK Resolution
000 001 010 011 100 101 524.3 [ms] 512.0 [ s] 16.0 [ s] 0.5 [ s] Reserved Reserved
16.0 MHz) 1
0
DV1CK Resolution
1.05 [s] 1.02 [ms] 32.0 [ s] 1.0 [ s] Reserved Reserved
Maximum time setting
9.54 [h] 33.6 [s] 1.05 [s] 32.8 [ms] Reserved Reserved
Maximum time setting
19.1 [h] 1.12 [min] 2.09 [s] 65.5 [ms] Reserved Reserved
Example: Sets the source clock fc/24 [Hz] and generates an interrupt event 25 ms (at fc 16 MHz, DV1CK 1) LDW (TC2DR), 61A8H ; Sets TC2DR (25 ms 24/fc 61A8H) DI SET (EIRH).6 ; Enable INTTC2 interrupt EI LD (TC2CR), 00001100B ; Selects TC2 source clock LD (TC2CR), 00101100B ; Starts TC2
Count start Source clock Up-Counter Timer register INTTC2 interrupt 0 1 2 3 4 n
n 1n0
1
2
3
Match detect
Counter clear
Figure 2.6.3 Timer Mode Timing Chart
88CS34-71
2003-03-25
TMP88CS34/CP34
(2) Event counter mode In this mode, events are counted on the rising edge of the TC2 pin input. The contents of TC2DR are compared with the contents of the up-counter. If a match is found, an INTTC2 interrupt is generated, and the counter is cleared. The minimum pulse width to the TC2 pin is shown in Table 2.6.2. Two or more machine cycles are required for both the "H" and "L" levels of the pulse width. Match detect is executed on the falling edge of the TC2 pin. A match can not be detected and INTTC2 is not generated when the pulse is still in a falling state. Example: Sets the event counter mode and generates an INTTC2 interrupt 640 counts later. LDW (TC2DR), 640 ; Sets TC2DR SET (EIRH). 6 ; Enables INTTC2 interrupt EI LD (TC2CR), 00011100B ; Selects TC2 source clock LD (TC2CR), 00111100B ; Starts TC2 Table 2.6.2 Timer/Counter 2 External Clock Source Minimum pulse width [S] NORMAL, IDLE mode
"H" width "L" width Count start TC2 pin input Up-counter Timer register INTTC2 interrupt 0 1 2 3 n
n 1 n 0
23/fc 23/fc
1
2
3
Match detect
Counter clear
Figure 2.6.4 Event Counter Mode Timing Chart
88CS34-72
2003-03-25
TMP88CS34/CP34
(3) Window mode In this mode, counting up performed on the rising edge of an internal clock during TC2 external pin input (window pulse) is "H" level. The contents of TC2DR are compared with the contents of up-counter. If a match found, an INTTC2 interrupt is generated, and the up-counter is cleared. The maximum applied frequency (TC2 input) must be considerably slower than the selected internal clock. Example: Generates an interrupt, inputting "H" level pulse width of 120 ms or more. (at fc 16.0 MHz, DV1CK 1) LDW (TC2DR), 0075H ; Sets TC2DR (120 ms 214/fc 0075H) DI SET (EIRH). 6 ; Enables INTTC2 interrupt EI LD (TC2CR), 00000101B ; Selects TC2 source clock LD (TC2CR), 00100101B ; Starts TC2
TC2 pin input Internal clock Up-counter TC2DR INTTC2 interrupt n Match detect Counter clear 0 1 2 n3 n 2
n1n0
1
2
3
Figure 2.6.5 Window Mode Timing Chart
88CS34-73
2003-03-25
TMP88CS34/CP34
2.7
8-Bit Timer/Counter3 (TC3B)
Configuration
Edge detector
TC3ES Rising TC3S Falling Clear INTTC3 interrupt
2.7.1
TC3 pin A Y B
fc/213 or fc/214 fc/212 or fc/213 fc/211 or fc/212 fc/210 or fc/211 fc/29 or fc/210 fc/28 or fc/29 fc/27 or fc/28
H A B C Y D E F G S
Source clock
8-bit up-counter
Overflow Comparator Match detect A B S
TC3S
Y
3
TC3CK ACAP TC3S
Capture TC3DRB TC3DRA 8-bit timer register
Capture
TC3M TC3CR TC3 control register
Note:
Propagation of control input/output requires the correct I/O port setting. For details, see the section on I/O pots.
Figure 2.7.1 Timer/Counter 3 (TC3)
88CS34-74
2003-03-25
TMP88CS34/CP34 2.7.2 Control
The timer/counter 3 is controlled by a timer/counter 3 control register (TC3CR) and two 8-bit timer registers (TC3DRA and TC3DRB) and port multiplex control register (PMPXCR).
TC3DRA (0018H) TC3DRB (0019H) TC3CR (001AH) 7 6 5 4 3 2 1 0 Read/Write (Initial value: 1111 1111) Read only (Initial value: 1111 1111) 7 6 ACAP TC3M 5 4 TC3S TC3 operating mode set 3 2 TC3K 1 0 TC3M (Initial value: *0*0 0000)
0: Timer/event counter 1: Capture NORMAL, IDLE mode DV1CK 000 001 fc/213 fc/212 fc/2 fc/2
11 10 9
0
DV1CK fc/214 fc/213 fc/212 fc/211 fc/2
10
1
TC3CK
TC3 source clock select [Hz]
010 011 100 101 110 111
fc/2 fc/2
Write only
fc/28
7
fc/29 fc/28
External clock (TC3 pin input)
TC3S ACAP Note 1: Note 2: Note 3:
TC3 start control Auto-capture control
0: Stop and clear 1: Start 0: 1: Auto-capture enable
fc: High-frequency clock [Hz], *: Don't care Set the mode and the source clock when the TC3 stops (TC3S 0).
Values to be loaded to timer register 3A must satisfy the following condition. TC3DRA 0 (in the timer and event counter mode)
Note 4: Note 5: Note 6:
Auto-capture can be used only in the timer and event counter mode. Before setting TC3DRA or switching the operating mode, stop the TC3 (TC3S 0).
When STOP mode is started, timer counter is stopped and TC3 start control (TC3S) is cleared to "0" automatically. Set TC3S to "1" after STOP mode is released for restarting timer counter.
Note 7: PMPXCR (0027H) 7
"0"
TC3CR, TCESCR is a write-only register and must not be used with any of read-modify-write instructions. 6
CHS
5
4
3
2
1
TC4ES
0
TC3ES
(Initial value: 00** **00) Write only
TC3ES Note 8:
TC3 input control Always write "0" to bit 7 in PMPXCR.
0: Normal 1: Invert
Figure 2.7.2 Timer Register 3 and TC3 Control Register
88CS34-75
2003-03-25
TMP88CS34/CP34 2.7.3 Function
The timer/counter 3 has three operating modes: timer, event counter, and capture mode. When it is used in the capture mode, the noise rejection time of TC3 pin input can be set by remote control receive control register. (1) Timer mode In this mode, the internal clock is used for counting up. The contents of TC3DRA are compared with the contents of up-counter. If a match is found, a timer/counter 3 interrupt (INTTC3) is generated, and the up-counter is cleared. The current contents of up-counter are loaded into TC3DRB by setting ACAP (bit6 in TC3CR) to "1" (Auto-capture function). The contents of up-counter can be easily confirmed by executing the read instruction (RD instruction) of TC3DRB. Loading the contents of up-counter is not synchronized with counting up. The contents of over flow (FFH) and 00H can not be loaded correctly. It is necessary to consider the count cycle.
Clock Counter TC3DRB FE FE FF 00 FF/00 01 01
Table 2.7.1 Source Clock (internal clock) for Timer/Counter 3 (Example: at fc NORMAL, IDLE mode TC3CK DV1CK Resolution [ s]
000 001 010 011 100 101 110 512 256 128 64 32 16 8
16.0 MHz)
0
DV1CK Resolution [ s]
1024 512 256 128 64 32 16
1
Maximum setting time [ms]
130.6 65.3 32.6 16.3 8.2 4.1 2.0
Maximum setting time [ms]
261.1 130.6 65.3 32.6 16.3 8.2 4.1
88CS34-76
2003-03-25
TMP88CS34/CP34
Count start Source clock Up-counter Timer register B INTTC3 interrupt ? 0 n Match detect Counter clear 1 2 3 4 n 1n0 1 2 3 4 5 6 7
(a) Timer Mode Source clock Up-counter Timer register B ACAP1 (b) Auto-capture m ? 2 m 1 m 1 m m1 Capture m m 1 m 2 m 2 n 1 n 1 n n1 Capture n n1
Figure 2.7.3 Timer Mode Timing Chart (2) Event counter mode In this mode, the TC3 pin input pulses are used for counting up Either the rising on falling edge can be selected with TC3ES (bit 0 in PMPXCR). The contents of TC3DRA are compared with the contents of the up-counter. If a match is found, an INTTC3 interrupt is generated and the counter is cleared. Match detect is executed on the falling edge of the TC3 pin. A match can not be detected, and INTTC3 is not generated when the pulse is still in a falling state. The maximum applied frequency is shown in Table 2.7.2. Two or more machine cycles are required for both the high and low levels of the pulse width. The current contents of up-counter are loaded into TC3DRB by setting ACAP (bit 6 in TC3CR) to "1" (Auto-capture funcion). The contents of up-counter can be easily confirmed by executing the read instruction (RD instruction) of TC3DRB. Loading the contents of up-counter is not synchronized with counting up. The contents of over flow (FFH) and 00H can not be loaded correctly. It is necessary to consider the count cycle. Example: Generates an interrupt every 0.5 s, inputting 50 Hz pulses to the TC3 pin. LD (TC3CR), 00001110B ; Sets TC3 mode and source clock LD (TC3DRA), 19H ; 0.5 s 1/50 25 19H LD (TC3CR), 00011100B ; Starts TC3 Table 2.7.2 Source Clock (External Clock) for Timer/Counter Minimum applied frequency [Hz] NORMAL, IDLE Mode
"H" width "L" width 22/fc 22/fc
88CS34-77
2003-03-25
TMP88CS34/CP34
Count start TC3 pin input Up-counter Timer register INTTC3 interrupt 0 1 2 3 n
n 1 n 0
1
2
3
Match detect
Counter clear
Figure 2.7.4 Event Counter Mode Timing Chart (3) Capture mode In this mode, the pulse width, period and duty of the TC3 pin input are measured in this mode, which can be used in decoding the remote control signals or distinguishing AC 50/60 Hz, etc. The TC3 pin input can have its polarity changed between normal and inverse by using the TC3ES Register. a. If TC3ES "0" (non-inverting input)
Once command operation has started, the counter free-runs on an internal source clock. When the falling edge of the TC3 pin input is detected, the counter value is loaded into TC3DRB. When the rising edge is detected, the counter value is loaded into TC3DRA, and the counter is cleared, generating an INTTC3 interrupt. If the rising edge is detected right after command operation has started, no capture to TC3DRB and an INTTC3 interrupt occurs only on capture to TC3DRA. If a read instruction is executed for TC3DRB, the value that exists at the end of the previous capture (immediately after a reset, "FF") is read. b. If TC3ES "1" (inverse input)
Once command operation has started, the counter free-runs on an internal clock. When the rising edge of the TC3 pin input is detected, the counter value is loaded into TC3DRB. When the falling edge is detected, the counter value is loaded into TC3DRA, and the counter is cleared, generating an INTTC3 interrupt. If the falling edge is detected right after command operation has started, the counter value is not captured into TC3DRB and an INTTC3 interrupt occurs only on capture to TC3DRA. If a read instruction is executed for TC3DRB, the value that exists at end of the previous capture (immediately after a reset, "FF") is read. The minimum acceptable input pulse width is equal to the length of one source clock period selected by TC3CR . Table 2.7.3 TC3INV-Based Capture Input Edges TC3ES
"0" (non-inverting input) "1" (inverting input)
Capture into TC3DRB
Falling edge Rising edge
Capture into TC3DRA
INTTC3 interrupt
Rising edge Falling edge
Note:
Capture of the TC3 pin input requires at least 1 cycle of the selected source clock.
88CS34-78
2003-03-25
Command start
TC3S
Source clock
0 i 1 i 1 k m 1 m 1 n 1 i 1k0 1 m 1n0 1 2 3 FE FF 1 2 3
Up-counter
TC3 pin input
Internal waveform (normal)
k n
TC3DRA
i capture capture m
FF (overflow)
FE
TC3DRB
overflow
INTTC3 interrupt
Reading TC3DRA a) In case of TC3ES Command start "0" (normal)
Figure 2.7.5 Capture Mode Timing Chart
88CS34-79
0 i k 1 k 1 m 1 i 0 1 k1 1m 0 1 n 3n i m k capture capture
TC3S
Source clock
2n 1n0 1 FE FF 1 2 3
Up-counter
TC3 pin input
Internal waveform (invert)
n
TC3DRA
TC3DRB
n
2 capture
2
INTTC3 interrupt
When TC3DRA is not read, capture and overflow detection are stopped.
Reading TC3DRA b) In case of TC3ES "1" (invert)
TMP88CS34/CP34
2003-03-25
TMP88CS34/CP34
The edge of TC3 pin input is detected in the remote control receive circuit with noize rejection. The remote control receive circuit is controlled by the remote control receive control register (RCCR). The romote control receive status register (RCSR) can monitor the porality selection and noize rejection circuit.
Rising TC3IN fc/28 or fc/29 TC3 Source clock RPOLS Polarity select MPX A BY S RCSCK 5 RCNF RCOVF RNCM Noise reject circuit (5-bit up-down counter) Edge detector Falling Capture control
RCNC
RCCR/RCSR MPX: Multiplexer Remote control receive control/status register
Figure 2.7.6 Remote Control Receiving Circuit
88CS34-80
2003-03-25
TMP88CS34/CP34
RCCR (00026H)
RCEN RCNC
RPOLS RCSCK Noise reject time select 02H RCNC 1FH Noise reject circuit Source clock select Remote control signal polarity select Remote control receive circuit operation control
RCNC (Source clock) (RCNC 1) [s]
(Initial value: 0001 1111) Write only DV1CK 29/fc TC3CK Note 2 1 R/W
NORMAL, IDLE mode RCSCK DV1CK 0 1 RPOLS RCEN Note 1: Note 2: Note 3: Note 4: Note 5: RCSR (00026H) 0: Positive 1: Negative 0: Disable 1: Enable 0) Write only 28/fc 0
Set RPOLS and RCSCK when the timer/counter stops (TC3S Source clock of timer/counter 3 fc: High-frequency clock [Hz], *: Don't care
RCCR includes a write-only register and must not be used with any of read-modify-write instructions. Values to be loaded to RCNC must satisfy the following condition. 02 RCNC 1F
RCNF RNCM
RPOLS RCSCK RCOVF
RNCM 0: Low level 1: High level
(Initial value: 0000 0***)
Remote control signal monitor after noise rejecter Noise reject circuit Overflow flag
RCOVF
0: Signal and definition by overwriting the noise reject time RCNC 1: Overflow NORMAL, IDLE mode DV1CK 0 1 0: Positive 1: Negative 0: Without noise 1: With noise 28/fc TC3CK Note 2 0 DV1CK 29/fc 1
Read only
RCSCK
Noise reject circuit Source clock select Remote control signal polarity select Remote control signal monitor after noise rejecter
R/W
RPOLS RCNF Note 1: Note 2: Note 3: Note 4:
Read only
Reading out the register RCSR resets RCNF and RCOVF. Source clock of timer/counter 3 When a 5-bit up-down counter counts down to "0" after counting up, the RCNF defines to be noise. fc: High-frequency clock [Hz], *: Don't care
Figure 2.7.7 Remote Control Receive Control Register and Remote Control Receive Status Register Table 2.7.4 Combination between The Polarity and The Edge Selection
RPOLS 0 TC3 pin input pulse (Interrupt occurrence is shown as allow.) Measurement
1
Note:
When TC3CK is used in RCSCK, do not select an external clock to the TC3CK.
88CS34-81
2003-03-25
Source clock 0 1 2 3 0 1 2 1 0
Up-down counter
TC3 pin input
RNCM
RCOVF
RCNF
Reset
Reading RCSR (a) Noise (RPOLS 0, RCNC 03H)
Source clock 0 1 2 3 4 0 1 2 1 0
Figure 2.7.8 Remote Control Receive Circuit Timing Chart
08H (b) Noise rejection circuit overflow flag (RPOLS 1, RCNC 08H to 03H) 03H
88CS34-82
Up-down counter
TC3 pin input
RNCM Reset
RCOVF
RCNF
Reading RCSR
Writing RCCR
RCNC
TMP88CS34/CP34
2003-03-25
TMP88CS34/CP34
2.8
8-Bit Timer/Counter 4 (TC4)
Configuration
2.8.1
TC4S fc/2 or fc/2 fc/27 or fc/28 fc/25 or fc/26 fc/23 or fc/24 TC4ES TC4 pin AS Y B
11 10
A B C D Y
Source clock
Clear 8-bit up-counter
Overflow detect
Comparator
H S 3 TC4CK TC4M 2
Match detect
TC4S
TC4CR Timer/Counter 4 Control Register
TC4DR 8-bit Timer Register 4
INTTC4 interrupt request signal
Note:
Set the input/output control correctly for the substitutive input/output pins. For details, see the description of the input/output port control register.
Figure 2.8.1 Timer/Counter 4 (TC4)
88CS34-83
2003-03-25
TMP88CS34/CP34 2.8.2 Control
The timer/counter 4 is controlled by a timer/counter 4 control register (TC4CR) and an 8-bit timer register 4 (TC4DR).
TC4DR (0001BH) TC4CR (0001CH) 7 7 6 6 5 5 TC4S 4 4 3 3 TC4CK 00: 01: 10: 11: 2 2 1 1 TC4M 0 Write only (Initial value: 1111 1111) 0 Write only (Initial value: **00 0000)
TC4S
TC4 start control
Timer/event counter mode Reserved Reserved Reserved NORMAL, IDLE mode DV1CK 0 DV1CK fs/212 fs/28 fs/26 fs/24 Reserved Reserved Reserved R/W 1
000 001 TC4CK TC4 source clock select [Hz] (Note 4) 010 011 100 101 110 111 00: 01: 10: 11:
fc/211 fc/27 fc/2 fc/2
5 3
Reserved Reserved Reserved Timer/event counter mode Reserved Reserved Reserved
External clock (TC4 pin input)
TC4M
TC4 operating mode select
Note 1: Note 2: Note 3:
fc: High-frequency clock [Hz], *; Don't care Values to be loaded to the timer register must satisfy the following condition. 1 When the TC4 is started (TC4S 1 0 1) or disabled (TC4S 1 TC4DR 255
0) or while the TC4 is operating (TC4S
1), do not write to TC4M and TC4CK in TC4CR. If these registers are selected/changed during these
operations, counting up is not performed properly. Note 4: When STOP mode is started, timer counter is stopped and cleared. Set TC4S to "1" after STOP mode is released for restarting timer counter. Note 5: Note 6: PMPXCR (00027H) TC4ES 7 "0" Undefined values are read from bits 6 and 7 of TC4CR. Do not change TC4DR while the TC4 is operating. 6 CHS 0: Rising edge 1: Falling edge 5 4 3 2 1 0
TC4ES (TC3ES) (Initial value: 00** **00) Write only
TC4 edge select Note 1:
TC4CR, TC4DR and PMPXCR are write only register and must not be used with any of the read-modify-write instructions such as SET, CLR, etc.
Figure 2.8.2 Timer Register 4 and TC4 Control Register
88CS34-84
2003-03-25
TMP88CS34/CP34 2.8.3 Function
The timer/counter 4 has two operating modes: timer, event counter mode. (1) Timer mode In this mode, the internal clock is used for counting up. The contents of TC4DR are compared with the contents of up-counter. If a match is found, an INTTC4 interrupt is generated and the up-counter is cleared to "0". Counting up resumes after the up-counter is cleared. Table 2.8.1 Source Clock (internal clock) for Timer/Counter 4 (Example: at fc NORMAL, IDLE mode TC4CK DV1CK Resolution [ s]
000 001 010 100 128.0 8.0 2.0 0.5
16.0 MHz) 1
0
DV1CK Resolution [ s]
256.0 16.0 4.0 1.0
Maximum setting time [ms]
32.6 2.0 0.510 0.128
Maximum setting time [ms]
65.3 4.1 1.0 0.255
(2) Event counter mode In this mode, the TC4 pin input (external clock) pulse is used for counting up. Either the rising or falling edge can be selected with TC4ES (bit 1 PMPXCR). The contents of TC4DR are compared with the contents of the up-counter. If a match is found, an INTTC4 interrupt is generated and the counter is cleared. The maximum applied frequency is shown Table 2.8.2. Two or more machine cycles are required for both the high and low level of the pulse width. Note: The event counter mode can only be used in NORMAL or IDLE mode. Table 2.8.2 Timer/Counter 4 External Clock Source Minimum input pulse width [s] NORMAL1, IDLE1 mode
"H" width "L" width 23/fc 23/fc
88CS34-85
2003-03-25
TMP88CS34/CP34
2.9
Serial Bus Interface (SBI-ver. D)
The TMP88CS34/CP34 has a 1-channel serial bus interface which employs a clocked-synchronous 8-bit serial bus interface and an I2C bus (a bus system by Philips). The serial bus interface pins are selectively used as either channel 0 or channel 1. The serial interface is connected to external devices through P35 (SDA0)/P52 (SDA1) and P34 (SCL0)/P51 (SCL1) in the I2C bus mode; and through P53 ( SCK1 ), P52 (SO1) and P51 (SI1) in the clocked-synchronous 8-bit SIO mode. The serial bus interface pins are also used for the P3/P5 port. When used for serial bus interface pins, set the P3/P5 output latches of these pins to "1". When not used as serial bus interface pins, the P3/P5 port is used as a normal I/O port. Note 1: When P3 and P5 is used as serial bus interface pins, P35, P34, P51 and P50 should be set as a sink open drain output by clearing PSELCR to "0". Note 2: The I C of TMP88CS34/CP34 can be used only in the Standard mode of I C. The Fast mode and the High Speed mode can not be used.
2 2
2.9.1
Configuration
INTSBI Interrupt Request SCL
SCK
P53 ( SCK )
SIO Clock Control fc/2 fc/4
P52 Input/ (SDA1/SO1) Output P51 Control (SCL1/SI1) SIO Data Control SO SI
Source Clock Generator
Divider Transfer Control Circuit
Noise Canceller
I2C bus Clock Sync. Control
Shift Register
I2C bus Data Control
Noise Canceller
SDA
P35 (SDA0) P34 (SCL0)
SBICRB/ SBISR
I2CAR
SBIDBR SBI data Buffer Register
SBICRA SBI Control Register A
SBI Control Register B/ I2C bus SBI Status Register Address Register
Figure 2.9.1 Serial Bus Interface (SBI)
88CS34-86
2003-03-25
TMP88CS34/CP34 2.9.2 Control
The following registers are used for control the serial bus interface and monitor the operation status. Serial bus interface control register A (SBICRA) Serial bus interface control register B (SBICRB) Serial bus interface data buffer register (SBIDBR) I2C bus address register (I2CAR) Serial bus interface status register A (SBISRA) Serial bus interface status register B (SBISRB) Serial clock source control register (SCCRB) Serial clock control status register (SCSR) The above registers differ depending on a mode to be used. Refer to Section "2.9.7 I2C bus mode control" and "2.9.9 Clocked-synchronous 8-bit SIO mode control".
2.9.3
Serial Clock Source Control
A serial bus interface circuit can reduce the power consumption by stopping a serial clock generater.
Serial Clock Source Control Register
SCCRB 7 SCEN SCEN Note: Serial clock source control 6 5 4 3 2 1 0 (Initial value: 0*** ****) 0: Do not generate source clock 1: Generate source clock Write only
(00FF1H)
When SCRQ and SCEN are "1", SCEN cannot be cleared to "0". When SCRQ is "0", SCEN is cleared to "0".
Serial Clock Control Status Register
SCSR 7 SCRQ SCRQ Serial clock source request 6 5 4 3 2 1 0 (Initial value: 0*** ****) 0: No source clock request from serial bus interface 1: Source clock request from serial bus interface Read only
(00FF1H)
SCRQ SCEN
Source clock Clock generation "1" SCEN Write data except "00" to SBIM "0" Write data "00" to SBIM SCEN
Figure 2.9.2 Serial Clock Source
88CS34-87
2003-03-25
TMP88CS34/CP34 2.9.4 Channel Select
A serial bus interface circuit can select I/O pin when a serial bus interface is used for I2C bus mode.
Port Switching register PMPXCR (00027H) 7 "0" CHS Note 1: Note 2: Note 3: 6 CHS I2C bus Channel Select 5 4 3 2 1 0
(TC4ES) (TC3ES) (Initial value: 00** **00) 0: Channel 0 1: Channel 1 R/W
When SIO mode, don't use channel 0. Therefore, set to "1" in PMPXCR at SIO mode. Always write "0" to bit 7 in PMPXCR. *: Don't care
Figure 2.9.3 Channel Select
2.9.5
Software Reset
A serial bus interface circuit has a software reset function, when a serial bus interface circuit is locked by an external noise, etc. To occur software reset, write "01", "10" into the SWRST (bit 1, 0 in SBICRB). During software reset, the SWRMON (bit 0 in SBISRA) is clear to "0".
2.9.6
The Data Format in The I2C bus Mode
The data format when using the TMP88CS34/CP34 in the I2C bus mode are shown in as below.
(a) Addressing format 8 bits S Slave address 1 (b) Addressing format (with restart) 8 bits S Slave address 1 (c) Free data format 8 bits S Data 1 Notes: S: Start condition R/ W : Direction bit ACK: Acknowledge bit P: Stop condition 1 A C K 1 to 8 bits Data 1 A C K 1 or more 1 to 8 bits Data 1 A CP K 1 RA /C WK 1 to 8 bits Data 1 or more 1 A CS K 8 bits Slave address 1 1 RA /C WK 1 to 8 bits Data 1 or more 1 A CP K 1 RA /C WK 1 to 8 bits Data 1 A C K 1 or more 1 to 8 bits Data 1 A CP K
Figure 2.9.4 Data Format in I C Bus Mode
2
88CS34-88
2003-03-25
TMP88CS34/CP34 2.9.7 I2C Bus Mode Control
The following registers are used to control the serial bus interface (SBI) and monitor the operation status in the I2C bus mode. Serial Bus Interface Control Register A
SBICRA (00020H) 7 6 BC 5 4 ACK 3 2 1 SCK ACK 0 Number of Bits Clock 8 8 1 1 2 2 3 3 4 4 5 5 6 6 7 7 Master mode Not generate a clock pulse for an acknowledgement. Generate a clock pulse for an acknowledgement. 0 (Initial value: 0000 *000) ACK 1 Number of Bits Clock 9 8 2 1 3 2 4 3 5 4 6 5 7 6 8 7 Slave mode Not count a clock pulse for an acknowledgement. Count a clock pulse for an acknowledgement.
BC 000 001 010 011 100 101 110 111 ACK 0
BC
Number of transferred bits
Write only
ACK
Acknowledgement mode specification
R/W
1
DV1CK 0 DV1CK 1 000: 200.0 kHz 000: 400.0 kHz 001: 111.1 kHz 001: 222.2 kHz 010: 58.8 kHz 010: 117.6 kHz Serial clock selection SCK 011: 30.3 kHz 011: 60.6 kHz (At fc 16 MHz, Output on SCL pin) 100: 15.4 kHz 100: 30.7 kHz 101: 7.7 kHz 101: 15.5 kHz 110: 3.9 kHz 110: 7.8 kHz 111 : Reserved 111 : Reserved Note 1: fc: High-frequency clock [Hz], *: Don't care Note 2: Set the BC to "000" before switching to 8-bit SIO bus mode. Note 3: SBICRA cannot be used with any of read-modify-write instructions such as bit manipulation, etc. Note 4: Do not set the SCK frequency to over 100 kHz in the I2C bus mode.
Write only
Serial Bus Interface Data Buffer Register
SBIDBR (00021H) 7 Note 1: Note 2: 6 5 4 3 2 1 0 (Initial value: **** ****) R/W
Note 3: Note 4:
For writing transmitted data, start from the MSB (bit 7). The data which was written into SBIDBR cannot be read, since a write data buffer and a read buffer are independent in SBIDBR. Therefore, SBIDBR cannot be used with any of read-modify-write instructions such as bit manipulation, etc. The data which was written into SBIDBR is cleared to "0" when INTSBI is generated. *: Don't care
I2C bus Address Register 7 I2CAR (00022H) SA6 SA ALS Note 1: Note 2:
6 SA5
4 3 Slave address SA4 SA3 SA2
5
2 SA1
1 SA0
0 ALS (Initial value: 0000 0000)
Slave address selection Write Address recognition mode 0: Slave address recognition only specification 1: Non slave address recognition I2CAR is write-only register and cannot be used with any of read-modify-write instruction such as bit manipulation, etc. Do not set I2CAR to "00H" to avoid the incorrect response of acknowledgment in slave mode. If "00H" is set to I2CAR as the Slave Address and received "01H" in slave mode, the device might transmit the acknowledgement incorrectly.
Figure 2.9.5 Serial Bus Interface Control Register A, Serial Bus Interface Data Buffer Register and I C Bus Address Register In The I C Bus Mode
2 2
88CS34-89
2003-03-25
TMP88CS34/CP34
Serial Bus Interface Control Register B
SBICRB (00023H) 7 MST MST TRX BB PIN 6 TRX 5 BB 4 PIN 3 SBIM 2 1 0 (Initial value: 0001 0000) SWRST1SWRST0
SBIM
0: 1: 0: Transmitter/Receiver selection 1: 0: Start/Stop generation 1: 0: Cancel interrupt service request 1: 00: 01: Serial bus interface operating mode selection 10: 11: Master/Slave selection
Slave Master Receiver Transmitter Generate a stop condition when MST, TRX and PIN are "1". Generate a start condition when MST, TRX and PIN are "1". Cancel interrupt service request Port mode (Serial bus interface output disable) Clocked synchronous 8-bit SIO mode I2C bus mode Reserved Write only
SWRST1 Software reset start bit SWRST0 Note 1: Note 2: Note 3: Note 4:
Software reset starts by first writing "10" and next writing "01".
Switch a mode to port after confirming that the bus is free. Switch a mode to I2C bus mode or clock synchronous 8-bit SIO mode after confirming that the port is high-level. SBICRB has write-only register and must not be used with any of read-modify-write instructions such as bit manipulation, etc. When the SWRST (bit 1, 0 in SBICRB) is written to "01", "10", software reset (four machine cycles) is occurred. This time, control the serial bus interface and monitor the operation status registers except the SBIM (bit 3, 2 in SBICRB) and the CHS (bit 6 in PMPXCR) are reseted. Control the serial bus interface and monitor the operation status registers are SBICRA, SBICRB, SBIDBR, I2CAR, SBISRA, SBISRB, SCCRA and SCSR.
Serial Bus Interface Status Register A
7 SBISRA (00020H) 6 5 4 ACK SWRMON Software reset monitor Note 1: *: Don't care 3 2 1 0 SWR MON 0: During software reset 1: (Initial) (Initial value: **** ***1) Read only
Serial Bus Interface Status Register B
SBISRB (00023H) 7 MST MST TRX BB PIN AL AAS AD0 LRB 6 TRX 5 BB 4 PIN 3 AL 2 AAS 0: Slave 1: Master 0: Receiver 1: Transmitter 0: Bus free 1: Bus busy 0: Requesting interrupt service 1: Releasing interrupt service request 0: 1: Arbitration lost detected 0: Not detect slave address match or "GENERAL CALL" 1: Detect slave address match or "GENERAL CALL" 0: Not detect "GENERAL CALL" 1: Detect "GENERAL CALL" 0: Last receive bit is "0" 1: Last receive bit is "1" Read only 1 AD0 0 LRB (Initial value: 0001 0000)
Master/Slave selection status monitor Transmitter/Receiver selection status monitor Bus status monitor Interrupt service requests status monitor Arbitration lost detection monitor Slave address match detection monitor "GENERAL CALL" detection monitor Last Received bit monitor
Figure 2.9.6 Serial Bus Interface Control Register B and Serial Bus Interface Status Register A/B in the I C Bus Mode
2
88CS34-90
2003-03-25
TMP88CS34/CP34
(1) Acknowledgement mode specification a. Acknowledgement mode (ACK "1")
To set the device as an acknowledgement mode, the ACK (bit4 in SBICRA) should be set to "1". When a serial bus interface circuit is a master mode, an additional clock pulse is generated for an acknowledge signal. In a slave mode, a clock is counted for the acknowledge signal. In the master transmitter mode, the SDA pin is released in order to receive an acknowledge signal from the receiver during additional clock pulse cycle. In the master receiver mode, the SDA pin is set to low level generation an acknowledge signal during additional clock pulse cycle. In a slave mode, when a received slave address matches to a slave address which is set to the I2CAR or when a "GENERAL CALL" is received, the SDA pin is set to low level generating an acknowledge signal. After the matching of slave address or the detection of "GENERAL CALL", in the transmitter the SDA pin is released in order to receive an acknowledge signal from the receiver during additional clock pulse cycle. In a receiver, the SDA pin is set to low level generation an acknowledge signal during additional clock pulse cycle after the matching of slave address or the detection of "GENERAL CALL". The Table 2.9.1 shows the SCL and SDA pins status in acknowledgement mode. Table 2.9.1 SCL and SDA Pins Status in Acknowledgement Mode Mode
Master
Pin
SCL SDA SCL
Transmitter
Released in order to receive and acknowledge signal.
Receiver
Set to low level generating an acknowledge signal.
An additional clock pulse is generated.
A clock is counted for the acknowledge signal. Set to low level generating an acknowledge signal. Released in order to receive an acknowledge signal. Set to low level generating an acknowledge signal.
Slave
SDA
When slave address matches or a general call is detected After matching of slave address or general call
b.
Non-acknowledgement mode (ACK
"0")
To set the device as a non-acknowledgement mode, the ACK should be cleared to "0". In the master mode, a clock pulse for an acknowledge signal is not generated. In the slave mode, a clock for a acknowledge signal is not counted. (2) Number of transfer bits The BC (bits 7 to 5 in SBICRA) is used to select a number of bits for next transmitting and receiving data. Since the BC is cleared to "000" as a start condition, a slave address and direction bit transmissions are always executed in 8 bits. Other than these, the BC retains a specified value.
88CS34-91
2003-03-25
TMP88CS34/CP34
(3) Serial clock a. Clock source The SCK (bits 2 to 0 in SBICRA) is used to select a maximum transfer frequency output from the SCL pin in the master mode. Four or more machine cycles are required for both high and low levels of pulse width in the external clock which is input from SCL pin. Note: Since the I2C of TMP88CS34/CP34 can not be used as the Fast mode and the High Speed mode, do not set SCK as the frequency that is over 100 kHz.
tHIGH tLOW 1/fscl
tLOW tHIGH fscl
2 /fc 2 /fc 1/(tLow
n
n
SCK (bits 2 to 0 in the SBICRA) 8/fc tHIGH) 000 001 010 011 100 101 110
n DV1CK 4 5 6 7 8 9 10 0 DV1CK 5 6 7 8 9 10 11 1
Note: fc: High-frequency clock
tSCKL tSCKH tSCKL , tSCKH 4 tcyc Note: tcyc 4/fc (in NORMAL mode, IDLE mode)
Figure 2.9.7 Clock Source b. Clock synchronization In the I2C bus mode, in order to drive a bus with a wired AND, a master device which pulls down a clock pulse to low will, in the first place, invalidate a clock pulse of another master device which generates a high-level clock pulse. The serial bus interface circuit has a clock synchronization function. This function ensures normal transfer even if there are two or more masters on the same bus. The example explains clock synchronization procedures when two masters simultaneously exist on a bus.
SCL pin (Master 1) SCL pin (Master 2) SCL (Bus) a Count reset
wait
Count start Count reset
b
c
Figure 2.9.8 Clock Synchronization As Master 1 pulls down the SCL pin to the low level at point "a", the SCL line of the bus becomes the low level. After detecting this situation, Master 2 resets counting a clock pulse in the high level and sets the SCL pin to the low level. Master 1 finishes counting a clock pulse in the low level at point "b" and sets the SCL pin to the high level. Since Master 2 holds the SCL line of the bus at the low level, Master 1 waits for counting a clock pulse in the high level. After Master 2 sets a clock
88CS34-92
2003-03-25
TMP88CS34/CP34
pulse to the high level at point "c" and detects the SCL line of the bus at the high level, Master 1 starts counting a clock pulse in the high level. Then, the master, which has finished the counting a clock pulse in the high level, pulls down the SCL pin to the low level. The clock pulse on the bus is deteminded by the master device with the shortest high-level period and the master device with the longest low-level period from among those master devices connected to the bus. (4) Slave address and address recognition mode specification When the serial bus interface circuit is used with an addressing format to recognize the slave address, clear the ALS (bit 0 in I2CAR) to "0", and set the SA (bits 7 to 1 in I2CAR) to the slave address. When the serial bus interfac circuit is used with a free data format not to recognize the slave address, set the ALS to "1". With a free data format, the slave address and the direction bit are not recognized, and they are processed as data from immediately after start condition. (5) Master/slave selection To set a master device, the MST (bit 7 in SBICRB) should be set to "1". To set a slave device, the MST should be cleared to "0". When a stop condition on the bus or an arbitration lost is detected, the MST is cleared to "0" by the hardware. (6) Transmitter/receiver selection To set the device as a transmitter, the TRX (bit 6 in SBICRB) should be set to "1". To set the device as a receiver, the TRX should be cleared to "0". When data with an addressing format is transferred in the slave mode, the TRX is set to "1" by a hardware if the direction bit (R/ W ) sent from the master device is "1", and is cleared to "0" by a hardware if the bit is "0. In the master mode, after an acknowledge signal is returned from the slave device, the TRX is cleared to "0" by a hardware if a transmitted direction bit is "1", and is set to "1" by a hardware if it is "0". When an acknowledge signal is not returned, the current condition is maintained. When a stop condition on the bus or an arbitration lost is detected, the TRX is cleared to "0" by the hardware. The following table show TRX changing conditions in each mode and TRX value after changing. Mode
Slave mode Master mode
Direction Bit
"0" "1" "0" "1"
Conditions
A received slave address is the same value set to I2CAR ACK signal is returned
TRX after Changing
"0" "1" "1" "0"
When a serial bus interface circuit operates in the free data format, a slave address and a direction bit are not recognized. They are handled as data just after generating a start condition. The TRX is not changed by a hardware.
88CS34-93
2003-03-25
TMP88CS34/CP34
(7) Start/Stop condition generation When the BB (bit 5 in SBICRB) is "0", a slave address and a direction bit which are set to the SBIDBR are output on a bus after generating a start condition by writing "1" to the MST, TRX, BB and PIN. It is necessary to set transmitted data to the SBIDBR and set "1" to ACK beforehand.
SCL pin
1 A6 Start condition
2 A5
3 A4
4 A3
5 A2
6 A1
7 A0
8
9
SDA pin
R/ W Acknowledge signal
slave address and the direction bit
Figure 2.9.9 Start Condition Generation and Slave Address Generation When the BB is "1", sequence of generating a stop condition is started by writeng "1" to the MST, TRX and PIN, and "0" to the BB. Do not modify the contents of MST, TRX, BB and PIN until a stop condition is generated on a bus.
SCL pin SDA pin Stop condition
Figure 2.9.10 Stop Condition Generation When a stop condition is generated and the SCL line on a bus is pulled-down to low level by another device, a stop condition is generated after releasing the SCL line. The bus condition can be indicated by reading the contents of the BB (bit 5 in SBISRB). The BB is set to "1" when a start condition on a bus is detected and is cleared to "0" when a stop condition is detected. (8) Interrupt service request and cancel When a serial bus interface circuit is in the master mode and transferring a number of clocks set by the BC and the ACK is complete, a serial bus interface interrupt request (INTSBI) is generated. In the slave mode, the conditions of generating INTSBI are follows: At the end of acknowledge signal when the received slave address matches to the value set by the I2CAR At the end of acknowledge signal when a "GENERAL CALL" is received At the end of transferring or receiving after matching of slave address or receiving of "GENRAL CALL" When a serial bus interface interrupt request occurs, the PIN (bit 4 in SBISR) is cleared to "0". During the time that the PIN is "0", the SCL pin is pulled-down to low level. Either writing data to SBIDBR or reading data from the SBIDBR sets the PIN to "1". The time from the PIN being set to "1" until the SCL pin is released takes tLOW. Although the PIN (bit 4 in SBICRB) can be set to "1" by the program, the PIN can not be cleared to "0" by the program. Note: If the arbitration lost occurs, when the slave address does not match, the PIN is not cleared to "0" even thought INTSBI is generated.
88CS34-94
2003-03-25
TMP88CS34/CP34
(9) Serial bus interface operating mode selection The SBIM (bit 3 and 2 in SBICRB) is used to specify a serial bus interface operation mode. Set the SBIM to "10" in order to change a operation mode to I2C bus mode. Before changing operation mode, confirm serial bus interface pins in a high level. And switch a mode to port after confirming that a bus is free. (10) Arbitration lost detection monitor Since more than one master device can exist simultaneously on a bus in the I2C bus mode, a bus arbitration procedure is implemented in order to guarantee the contents of transferred data. Data on the SDA line is used for bus arbitration of the I2C bus. The following shows an example of a bus arbitration procedure when two master devices exist simultaneously on a bus. Master 1 and Master 2 output the same data until point " a". After Master 1 outputs "1" and Master 2, "0", the SDA line of a bus is wired AND and the SDA line is pulled-down to the low level by Master 2. When the SCL line of a bus is pulled-up at point "b", the slave device reads data on the SDA line, that is data in Master 2. Data transmitted from Master 1 becomes invalid. The state in Master 1 is called "arbitration lost". A master device which loses arbitration releases the SDA pin and the SCL pin in order not to effect data transmitted from other masters with arbitration. When more than one master sends the same data at the first word, arbitration occurs continuously after the second word.
SCL (Bus)
SDA pin (Master 1) SDA pin becomes "1" after losing arbitration. SDA pin (Master 2)
SDA (Bus) a b
Figure 2.9.11 Arbitration Lost
88CS34-95
2003-03-25
TMP88CS34/CP34
The serial bus interface circuit compares levels of a SDA line of a bus with its those SDA pin at the rising edge of the SCL line. If the levels are unmatched, arbitration is lost and the AL (bit 3 in SBISRB) is set to "1". When the AL is set to "1", the MST and TRX are cleared to "0" and the mode is switched to a slave receiver mode. The AL is cleared to "0" by writing or reading data to or from the SBIDBR or writing data to the SBICRB.
SCL pin Master A SDA pin D7A D6A D5A D4A D3A D2A D1A D0A D7A' D6A' D5A' 1 2 3 4 5 6 7 8 9 1 2 3
SCL pin Master B SDA pin
1 D7B
2 D6B
3
4
5
6
7
8
9
Stop clock output Releasing SDA pin and SCL pin to high level as losing arbitration.
AL
MST
TRX Accessed to SBIDBR or SBICRB INTSBI
Figure 2.9.12 Example of when a Serial Bus Interface Circuit is a Master B (11) Slave address match detection monitor In the slave mode, the AAS (bit 2 in SBISR) is set to "1" when the received data is "GENERAL CALL" or the received data matches the slave address setting by I2CAR with an address recognition mode (ALS 0). When a serial bus interface circuit operates in the free data format (ALS set to "1" after receiving the first 1-word of data. 1), the AAS is
The AAS is cleared to "0" by writing data to the SBIDBR or reading data from the SBIDBR. (12) GENERAL CALL detection monitor The AD0 (bit 1 in SBISR) is set to "1" when all 8-bit received data is "0" immediately after a start condition in a slave mode. The AD0 is cleared to "0" when a start or stop condition is detected on a bus. (13) Last received bit monitor The SDA value stored at the rising edge of the SCL is set to the LRB (bit0 in SBISRB). In the acknowledge mode, immediately after an INTSBI interrupt request is generated, an acknowledge signal is read by reading the contents of the LRB.
88CS34-96
2003-03-25
TMP88CS34/CP34 2.9.8 Data Transfer of I2C Bus
For initialization of device, set the ACK in SBICRA to "1" and the BC to "000". Specify the data length to 8 bits to count clocks for an acknowledge signal. Set a transfer frequency to the SCK in SBICRA. Next, set the slave address to the SA in I2CAR and clear the ALS to "0" to set an addressing format. After confirming that the serial bus interface pin is high-level, for specifying the default setting to a slave receiver mode, clear "0" to the MST, TRX and BB in SBICRB, set "1" to the PIN, "10" to the SBIM, and "00" to bits SWRST1 and SWRST0. Note: The initialization of a serial bus interface circuit must be complete within the time from all devices which are connected to a bus have initialized to and device does not generate a start condition. If not, the data can not be received correctly because the other device starts transferring before an end of the initialization of a serial bus interface circuit.
(1) Device initialization
(2) Start condition and slave address generation Confirm a bus free status (when BB 0). Set the ACK to "1" and specify a slave address and a direction bit to be transmitted to the SBIDBR. By writing "1" to the MST, TRX, BB and PIN, the start condition is generated on a bus and then, the slave address and the direction bit which are set to the SBIDBR are output. An INTSBI interrupt request occurs at the 9th falling edge of a SCL clock cycle, and the PIN is cleared to "0". The SCL pin is pulled-down to the low level while the PIN is "0". When an interrupt request occurs the TRX changes by the hardware according to the direction bits only when an acknowledge signal is returned from the slave device. Note 1: Do not write a slave address to be output to the SBIDBR while data is transferred. If data is written to the SBIDBR, data to been outputting may be destroyed. Note 2: The bus free must be confirmed by software within 98.0 s (the shortest transmitting 2 time according to the I C bus standard) after setting of the slave address to be output. Only when the bus free is confirmed, set "1" to the MST, TRX, BB, and PIN doesn't finish within 98.0 s, the other masters may start the transferring and the slave address data written in SBIDBR may be broken.
SCL pin 1 2 3 4 5 6 7 8 9
SDA pin
A6 Start condition
A5
A4
A3
A2
A1
A0
R/ W Acknowledge signal from a slave device
Slave address PIN INTSBI interrupt request
direction bit
Figure 2.9.13 Start Condition Generation and Slave Address Transfer
88CS34-97
2003-03-25
TMP88CS34/CP34
(3) 1-word data transfer Check the MST by the INTSBI interrupt process after an 1-word data transfer is completed, and determine whether the mode is a master or slave. a. When the MST is "1" (Master mode) Check the TRX and determine whether the mode is a transmitter or receiver. 1. When the TRX is "1" (Transmitter mode) Test the LRB. When the LRB is "1", a receiver does not request data. Implement the process to generate a stop condition (described later) and terminate data transfer. When the LRB is "0", the receiver requests next data. When the next transmitted data is other than 8 bits, set the BC, set the ACK to "1", and write the transmitted data to the SBIDBR. After writing the data, the PIN becomes "1", a serial clock pulse is generated for transferring a next 1-word of data from the SCL pin, and then the 1-word data is transmitted. After the data is transmitted, and an INTSBI interrupt request occurs. The PIN become "0" and the SCL pin is set to low level. If the data to be transferred is more than one word in length, repeat the procedure from the LRB test above.
Write to SBIDBR SCL pin 1 D7 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 Acknowledge signal from a receiver 9
SDA pin
PIN
INTSBI interrupt request
Figure 2.9.14 Example of when BC 2. When the TRX is "0" (Receiver mode)
"000", ACK
"1"
When the next transmitted data is other than of 8 bits, set the BC again. Set the ACK to "1" and read the received data from the SBIDBR (reading data is undefined immediately after a slave address is sent). After the data is read, the PIN becomes "1". A serial bus interface circuit outputs a serial clock pulse to the SCL to transfer next 1-word of data and sets the SDA pin to "0" at the acknowledge signal timing. An INTSBI interrupt request occurs and the PIN becomes "0". Then a serial bus interface circuit outputs a clock pulse for 1-word of data transfer and the acknowledge signal each time that received data is read from the SBIDBR.
Read to SBIDBR SCL pin 1 D7 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 9 New D7 Acknowledge signal to a transmitter
SDA pin
PIN
INTSBI interrupt
Figure 2.9.15 Example of when BC
"000", ACK
"1"
88CS34-98
2003-03-25
TMP88CS34/CP34
To make the transmitter terminate transmit, clear the ACK to "0" before reading data which is 1-word before the last data to be received. A serial bus interface circuit does not generate a clock pulse for the acknowledge signal by clearing ACK. In the interrupt routine of end of transmission, when the BC is set to "001" and read the data, PIN is set to "1" and generates a clock pulse for a 1-bit data transfer. In this case, since the master device is a receiver, the SDA line on a bus keeps the high-level. The transmitter receives the high-level signal as an ACK signal. The receiver indicates to the transmitter that data transfer is complete. After 1-bit data is received and an interrupt request has occurred, generates the stop condition to terminate data transter.
SCL pin
1 D7
2 D6
3 D5
4 D4
5 D3
6 D2
7 D1
8 D0
1
SDA pin
Acknowledge signal sent to a transmitter PIN
INTSBI interrupt request "0" ACK Read SBIDBR
"001" BC Read SBIDBR
Figure 2.9.16 Termination of Data Transfer in Master Receiver Mode b. When the MST is "0" (Slave mode) In the slave mode, a serial bus interface circuit operates either in normal slave mode or in slave mode after losing arbitration. In the slave mode, the conditions of generating INTSBI are follows: When the received slave address matches to the value set by the I2CAR When a "GENERAL CALL" is received At the end of transferring or receiving after matching of slave address or receiving of "GENERAL CALL" A serial bus interface circuit changes to a slave mode if arbitration is lost in the master mode. And an INTSBI interrupt request occurs when word data transfer terminates after losing arbitration. The behavior of INTSBI and PIN after losing arbitration are shown in Table 2.9.2. Table 2.9.2 The Behavior of INTSBI and PIN after Losing Arbitration
When the arbitration occurs during transmission of slave address as a master INTSBI PIN When the slave address matches the value set by I2CAR, the PIN is cleared to "0" by generating of INTSBI. When the slave address doesn't match the value set by I2CAR, the PIN keeps "1". When the arbitration occurs during transmission of data as a master transmit mode PIN keeps "1".
INTSIB is generated at the terminatin of word data.
Check the AL (bit 3 in the SBISR), the TRX (bit 6 in the SBISR), the AAS (bit 2 in the SBISR), and the AD0 (bit 1 in the SBISR) and implements processes according to conditions listed in Table 2.9.3.
88CS34-99
2003-03-25
TMP88CS34/CP34
Table 2.9.3 Operation in the Slave Mode TRX
1
AL
1
AAS
1
AD0
0
Conditions
A serial bus interface circuit loses arbitration when transmitting a slave address. And receives a slave address of which the value of the direction bit sent from another master is "1". In the slave receiver mode, a serial bus interface circuit receives a slave address of which the value of the direction bit sent from the master is "1". In the slave transmitter mode, 1-word data is transmitted.
Process
Set the number of bits in 1 word to the BC and write transmitted data to the SBIDBR.
0
1
0
0
0
Test the LRB. If the LRB is set to "1", set the PIN to "1" since the receiver does not request next data. Then, clear the TRX to "0" release the bus. If the LRB is set to "0", set the number of bits in 1-word to the BC and write transmitted data to the SBIDBR since the receiver requests next data. Read the SBIDBR for setting the PIN to "1" (reading dummy data) or write "1" to the PIN.
0
1
1
1/0
A serial bus interface circuit loses arbitration when transmitting a slave address. And receives a slave address of which the value of the direction bit sent from another master is "0" or receives a "GENERAL CALL". A serial bus interface circuit loses arbitration when transmitting a slave address or data. And terminates transferring word data. In the slave receiver mode, a serial bus interface circuit receives a slave address of which the value of the direction bit sent from the master is "0" or receives "GENERAL CALL". In the slave receiver mode, a serial bus interface circuit terminates receiving of 1-word data.
0
0
A serial bus interface circuit is changed to slave mode. To clear AL to "0", read the SBIDBR or write the data to SBIDBR. Read the SBIDBR for setting the PIN to "1" (reading dummy data) or write "1" to the PIN.
0
1
1/0
0
1/0
Set the number of bits in 1-word to the BC and read received data from the SBIDBR.
Note: In the slave mode, if the slave address set in I2CAR is "00000000B", the TRX changes to "1" by receiving the start byte data "00000001B".
(4) Stop condition generation When the BB is "1", a sequence of generating a stop condition is started by setting "1" to the MST, TRX, and PIN, and clear "0" to the BB. Do not modify the contents of the MST, TRX, BB, PIN until a stop condition is generated on a bus. When a SCL line on a bus is pulled-down by other devices, a serial bus interface circuit generates a stop condition after they release a SCL line.
"1" "1" "0" "1" MST TRX BB PIN
Stop condition
SCL pin SDA pin
PIN BB (Read)
Figure 2.9.17 Stop Condition Generation
88CS34-100
2003-03-25
TMP88CS34/CP34
(5) Restart Restart is used to change the direction of data transfer between a master device and a slave device during transferring data. The following explains how to restart a serial bus interface circuit. Clear "0" to the MST, TRX and BB and set "1" to the PIN. The SDA pin retains the high-level and the SCL pin is released. Since a stop condition is not generated on a bus, a bus is assumed to be in a busy state from other devices. Test the BB until it becomes "0" to check that the SCL pin a serial bus interface circuit is released. Test the LRB until it becomes "1" to check that the SCL line on a bus is not pulled-down to the low-level by other devices. After confirming that a bus stays in a free state, generate a start condition with procedure (2). In order to meet setup time when restarting, take at least 4.7 s of waiting time by software from the time of restarting to confirm that a bus is free until the time to generate a start condition. Note: When restarting after receiving in master receiver mode, because the divice doesn't send an acknowledgement as a last data, the level of SCL line can not be conrirmied by reading LRB. Therefore, confirm the status of SCL line by reading P5PRD register.
"0" "0" "0" "1" MST TRX BB PIN "1" "1" "1" "1" MST TRX BB PIN Start condition
4.7 s (Min) SCL (Bus) SCL (pin) SDA (pin) LRB BB PIN
Figure 2.9.18 Timing Diagram when Restarting
88CS34-101
2003-03-25
TMP88CS34/CP34 2.9.9 Clocked-synchronous 8-Bit SIO Mode Control
The following registers are used to control the serial bus interface (SBI) and monitor the operation in the clocked-synchronous 8-bit SIO mode. Serial Bus Interface Control Register A
SBICRA (00020H) 7 SIOS SIOS SIOINH 6 SIOINH 5 SIOM 4 3 "0" 0: 1: 0: 1: 00: 01: 10: 11: 2 1 SCK 0 (Initial value: 0000 *000)
Indicate transfer start/stop Continue/abort transfer
SIOM
Transfer mode select
Stop Start Continue transfer Abort transfer (automatically cleared after abort) 8-bit transmit mode reserved 8-bit transmit/receive mode 8-bit receive mode DV1CK 1 000: 500.0 kHz 001: 250.0 kHz 010: 125.0 kHz 011: 62.5 kHz 100: 31.2 kHz 101: 15.6 kHz 110: 7.8 kHz 111: External clock (Input from SCK pin) Write only
SCK
Serial clock selection (At fc 16 MHz, Output on SCK pin)
DV1CK 0 000: 1000.0 kHz 001: 500.0 kHz 010: 250.0 kHz 011: 125.0 kHz 100: 62.5 kHz 101: 31.2 kHz 110: 15.6 kHz 111: External clock (Input from SCK pin)
Note 1: Note 2: Note 3:
fc: High-frequency clock [Hz], *: Don't care Clear the SIOS to "0" and set the SIOINH to "1" when setting the transfer mode and serial clock. SBICRA is write-only register and cannot be used with any of read-modify-write instructions such as bit manipulation, etc. 6 5 4 3 2 1 0 (Initial value: **** ****) R/W
Serial Bus Interface Data Register
SBIDBR (00021H) 7 Note1 :
The data which was written into SBIDBR cannot be read, since a write buffer and a read buffer are independent in SBIDBR. Therefore, SBIDBR cannot be used with any of read-modify-write instructions such as bit manipulation, etc. Note 2: *: Don't care
Serial Bus Interface Control Register B
SBICRB (00023H) 7 "0" 6 "0" 5 "0" 4 "1" 3 SBIM 00: 01: 10: 11: 2 1 0 (Initial value: **** 0000)
SWRST1 SWRST0
SBIM
Serial bus interface operation mode selection
Port mode (serial bus interface output disable) SIO mode I2C bus mode reserved
Write only
SWRST1 Software reset start bit SWRST0 Note 1: Note 2: Note 3: Note 4: Note 5: Note 6:
Software reset starts by first writing "10" and next writing "01"
*: Don't care Switch a mode to port after data transfer is complete. Switch a mode to I2C bus mode or clock synchronous 8-bit SIO mode after confirming that the port is high-level. SBICRB is a write-only register and cannot be used with any of read-modify-write instructions such as bit manipulation, etc. Clear bit 7 to 5 in SBICRB to "0", and set bit 4 to "1". When the SWRST (bit 1, 0 in SBICRB) is written to "01", "10", software reset is occurred. This time, control the serial bus interface and monitor the operation status registers except the SBIM (bit 3, 2 in SBICRB) and the CHS (bit 6 in PMPXCR) are reseted. Control the serial bus interface and monitor the operation status registers are SBICRA, SBICRB, SBIDBR, I2CAR, SBISRA, SBISRB, SCCRA, SCCRB and SCSR.
Figure 2.9.19 Control Register/Data Buffer Register/Status Register in SIO Mode (1)
88CS34-102
2003-03-25
TMP88CS34/CP34
Serial Bus Interface Status Register A
SBISRA (00020H) 7 6 5 4 3 2 1 0 SWR MON SWRMON Software reset monitor 0: During software reset 1: (Initial) (Initial value: **** ***1) Read only
Serial Bus Interface Status Register B
SBISRB (00023H) 7 "1" SIOF SEF Note: 6 "1" 5 "1" 4 "1" 3 SIOF 2 SEF 1 "1" 0 "1"
Serial transfer operating status monitor Shift operating status monitor
0: Transfer terminated 1: Transfer in process 0: Shift operation terminated 1: Shift operation in process
Read only
Set bit 7 to 4, bit 1 and bit 0 in SBISRB to "1".
Figure 2.9.20 Control Register/Data Buffer Register/Status Register in SIO Mode (2) (1) Serial clock a. Clock source The SCK (bits 2 to 0 in SBICRA) is used to select the following functions. 1. Internal clock In an internal clock mode, any of seven frequencies can be selected. The serial clock is output to the outside on the SCK pin. The SCK pin becomes a high-level when data transfer starts. When writing (in the transmit mode) or reading (in the receive mode) data cannot follow the serial clock rate, an automatic-wait function is executed to stop the serial clock automatically and hold the next shift operation until reading or writing is complete.
Automatic-wait function
SCK pin output
1 a0 a
2 a1
3 a2 a5
7 a6
8 a7
1 b0 b
2 b1 c
6
7
8
1
2
3 c2
SO pin output Write transmitted data
b4 b5 b6 b7 c0 c1
Figure 2.9.21 Automatic Wait Function 2. External (SCK "111")
An external clock supplied to the SCK pin is used as the serial clock. In order to ensure shift operation, a pulse width of at least 4-machine cycles is required for both high and low levels in the serial clock. The maximum data transfer frequency is 500 KHz (fc 16.0 MHz).
SCK pin
tSCKL tSCKH tSCKL, tSCKH 4 tcyc
Note: tcyc
4/fc (in NORMAL mode, IDLE mode)
Figure 2.9.22 The Maximum Data Transfer Frequency in The External Clock Input
88CS34-103
2003-03-25
TMP88CS34/CP34
b. Shift edge The leading edge is used to transmit data, and the trailing edge is used to receive data. 1. Leading edge Data is shifted on the leading edge of the serial clock (at a falling edge of the SCK pin input/output). 2. Trailing edge Data is shifted on the trailing edge of the serial clock (at a rising edge of the SCK pin input/output).
SCK pin
SO pin Shift register
Bit 0
Bit 1
Bit 2
Bit 3
***76543
Bit 4
****7654
Bit 5
*****765
Bit 6
******76
Bit 7
*******7
76543210 *7654321 **765432
(a) Leading edge
SCK pin
SI pin Shift register
Bit 0
********
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
0*******
10******
210*****
3210****
43210***
543210** 6543210* 76543210
(b) Trailing edge
*: Don't care
Figure 2.9.23 Shift Edge (2) Transfer mode The SIOM (bits 5 and 4 in SBICRA) is used to select a transmit, receive, or transmit/receive mode. a. 8-bit transmit mode Set a control register to a transmit mode and write transmit data to the SBIDBR. After the transmit data is written, set the SIOS to "1" to start data transfer. The transmitted data is transferred from the SBIDBR to the shift register and output to the SO pin in synchronous with the serial clock, starting from the least significant bit (LSB). When the transmit data is transferred to the shift register, the SBIDBR becomes empty. The INTSBI (buffer empty) interrupt request is generated to request new data. When the internal clock is used, the serial clock will stop and automatic-wait function will be initiated if new data is not loaded to the data buffer register after the specified 8-bit data is transmitted. When transmit new data is written, automatic-wait function is canceled. When the external clock is used, data should be written to the SBIDBR before new data is shifted. The SO pin is "1" from the time transmission starts until the first data bit is sent. When SIOF becomes "0", the shift register is cleared. So, output of an undefined value is not prevented at the start of the next transmission. The transfer speed is determined by the maximum delay time between the time when an interrupt request is generated and the time when data is written to the SBIDBR by the interrupt service program.
88CS34-104
2003-03-25
TMP88CS34/CP34
Transmitting data is ended by cleaning the SIOS to "0" by the buffer empty interrupt service program or setting the SIOINH to "1". When the SIOS is cleared, the transmitted mode ends when all data is output. In order to confirm if data is surely transmitted by the program, set the SIOF (bit 3 in the SBISRB) to be sensed. The SIOF is cleared to "0" when transmitting is complete. When the SIOINH is set, transmitting data stops. The SIOF turns "0". When the external clock is used, it is also necessary to clear the SIOS to "0" before new data is shifted; otherwise, dummy data is transmitted and operation ends.
Clear SIOS SIOS SIOF SEF
SCK pin (output)
SO pin INTSBI interrupt request SBIDBR a
a0
a1
a2
a3
a4
a5
a6
a7
b0
b1
b2
b3
b4
b5
b6
b7
b
Write transmitted data
(a) Internal clock Clear SIOS
SIOS SIOF SEF
SCK pin (input)
SO pin INTSBI interrupt request SBIDBR a
a0
a1
a2
a3
a4
a5
a6
a7
b0
b1
b2
b3
b4
b5
b6
b7
b
Write transmitted data
(b) External clock
Figure 2.9.24 Transfer Mode
88CS34-105
2003-03-25
TMP88CS34/CP34
Example: Program to stop transmitting data. (When external clock is used) STEST1: TEST (SBISRB) . SEF ; If SEF 1 then loop JRS F, STEST1 STEST2: TEST (P5) . 3 ; If SCK 0 then loop JRS T, STEST2 LD (SBICRA) , 00000111B ; SIOS 0
SCK pin
SIOF
SO pin
Bit 6
Bit 7
tSODH
Min 3.5/fc [s] (In normal mode, IDLE mode)
Figure 2.9.25 Transmitted Data Hold Time at End of Transmit b. 8-bit receive mode Set a control register to a receive mode and the SIOS to "1" for switching to a receive mode. Data is received from the SI pin to the shift register in synchronous with the serial clock, starting from the least significant bit (LSB). When the 8-bit data is received, the data is transferred from the shift register to the SBIDBR. The INTSBI (buffer full) interrupt request is generated to request of reading the received data. The data is read from the SBIDBR by the interrupt service program. When the external clock is used, since shift operation is synchronized with the clock pulse provided externally, the received data should be read from SBIDBR before next serial clock is input. If the received data is not read, further data to be received is canceled. When the internal clock is used, the automatic wait function is executed until received data is read from SBIDBR. The maximum transfer speed when the external clock is used is determined by the delay time between the time when an interrupt request is generated and the time when received data is read. Received data disappears if this data is not completely read before reception of the next data terminates. In this case, the next data received is read. Receiving data is ended by clearing the SIOS to "0" by the buffer full interrupt service program or setting the SIOINH to "1". When the SIOS is cleared, received data is transferred to the SBIDBR in complete blocks. The received mode ends when the transfer is complete. In order to confirm if data is surely received by the program, set the SIOF (bit 3 in SBIDBR) to be sensed. The SIOF is cleared to "0" when receiving is complete. After confirming that receiving has ended, the last data is read. When the SIOINH is set, receiving data stops. The SIOF turns "0" (the received data becomes invalid, therefore no need to read it). Note: When the transfer mode is switched, the SBIDBR contents are lost. In case that the mode needs to be switched, receiving data is concluded by clearing the SIOS to "0", read the last data, and then switch the mode.
88CS34-106
2003-03-25
TMP88CS34/CP34
Clear SIOS SIOS SIOF SEF
SCK pin (output)
SI pin INTSBI interrupt request SBIDBR
a0
a1
a2
a3
a4
a5
a6
a7
b0
b1
b2
b3
b4
b5
b6
b7
a Read received data
b Read received data
Figure 2.9.26 Receive Mode (Example: Internal clock)
88CS34-107
2003-03-25
TMP88CS34/CP34
c. 8-bit transmit/receive mode Set a control register to a transmit/receive mode and write data to the SBIDBR. After the data is written, set the SIOS to "1" to start transmitting/receiving. When transmitting, the data is output from the SO pin on the leading edges in synchronous with the serial clock, starting from the least significant bit (LSB). When receiving, the data is input to the SI pin on the trailing edges of the serial clock. 8-bit data is transferred from the shift register to the SBIDBR, and the INTSBI interrupt request occurs. The interrupt service program reads the received data from the data buffer register and writes data to be transmitted. The SBIDBR is used for both transmitting and receiving. Transmitted data should always be written after received data is read. When the internal clock is used, automatic-wait function is initiated until received data is read and next data is written. When the external clock is used, since the shift operation is synchronized with the external clock, received data is read and transmitted data is written before new shift operation is executed. The maximum transfer speed when the external clock is used is determined by the delay time between the time when an interrupt request is generated and the time when received data is read and transmitted data is written. When transmission starts, a value which is the same as the last bit of previously transmitted data is output from the time SIOF is set to "1" until the falling edge of SCK occurs. Transmitting/receiving data is ended by cleaning the SIOS to "0" by the INTSBI interrupt service program or setting the SIONH to "1". When the SIOS is cleared, received data is transferred to the SBIDBR in complete blocks. The transmit/receive mode ends when the transfer is complete. In order to confirm if data is surely transmitted/received by the program, set the SIOF (bit 3 in SBISRB) to be sensed. The SIOF becomes "0" after transmitting/receiving is complete. When the SIONH is set, transmitting/receiving data stops. The SIOF turns "0". Note: When the transfer mode is switched, the SBIDBR contents are lost. In case that the mode needs to be switched, conclude transmitting/receiving data by clearing the SIOS to "0", read the last data, and then switch the transfer mode.
Clear SIOS SIOS
SIOF SEF
SCK pin (output)
SO pin SI pin INTSBI interrupt request SBIDBR a
a0 c0
a1 c1
a2 c2
a3 c3
a4 c4
a5 c5
a6 c6
a7 c7
b0 d0
b1 d1
b2 d2
b3 d3
b4 d4
b5 d5
b6 d6
b7 d7
c
b
d Read received data (d)
Write transmitted data (a)
Read received Write transmitted data (c) data (b)
Figure 2.9.27 Transmit/Receive Mode (Example: Internal clock)
88CS34-108
2003-03-25
TMP88CS34/CP34
SCK pin
SIOF SO pin Bit 6 Bit 7 in last transmitted word
tSODH
Min 4/fc [s] (In normal mode, idle mode)
Figure 2.9.28 Transmitted Data Hold Time at End of Transmit/Receive
88CS34-109
2003-03-25
TMP88CS34/CP34
2.10 Remote Control Signal Preprocessor/External Interrupt 3 Input Pin
The remote control signal waveform can be determined by inputting the remote control signal waveform from which the carrier wave was eliminated by the receive circuit to P30 (INT3/RXIN) pin. When the remote control signal preprocessor/external interrupt 3 pin is also used as the P30 port, set the P30 port output latch to "1". When it is not used as the remote control signal preprocessor/external interrupt 3 input pin, it can be used for normal port.
2.10.1
Configuration
fc/211 fc/210 fc/28 fc/27 fc/26 fc/25 fc/22 Selector RNC Polarity select Interrupt select INT. EINT Measurement width select Selector fc/26 fc/28 fc/210 fc/212 2 RCCK RXCR1 Remote control receive control register 1 RMM 4 RCS CREGA RXCR2 Remote control receive control register 2 8-bit upcounter Remote control receive counter register (RXCTR) Match detect SRM Shift register INT3 Interrupt request
Receive bit counter
Receive bit counter value monitor (RBCTM)
INT3/RXIN
Noise canceller to
RNCM
23 RPOLS
2
Remote control receive data buffer register (RXDBR)
Figure 2.10.1 Remote Control Signal Preprocessor
2.10.2
Remote Control Signal Preprocessor Control
When the remote control signal preprocessor is used, operating states are controlled and monitored by the following registers. Interrupt requests also use the remote control signal preprocessor/external interrupt 3 input pin. Remote control receive control register 1 (RXCR1) Remote control receive control register 2 (RXCR2) Remote control receive counter register (RXCTR) Remote control receive data buffer register (RXDBR) Remote control receive status register (RXSR) When this pin is used for the external interrupt 3 input, set EINT in RXCR1 to other than "11".
88CS34-110
2003-03-25
TMP88CS34/CP34
Remote control receive control register 1
RXCR1 (00FE8H) 7 RCCK 6 5 RPOLS 4 EINT 00: 01: 10: 11: 0: 1: 00: 01: 10: 11: 001: 010: 011: 100: 101: 110: 111: 000:
6
3
2
1 RNC
0 (Initial value: 0000 0000)
RCCK
8-bit up-counter source clock select Remote control signal polarity select
fc/2 (Hz) fc/28 fc/210 fc/212 Positive Negative Rising edge Falling edge (at RPOLS Rising/Falling edge 8-bit receive end 22/fc 7 1/fc (s) 25/fc 7 1/fc 26/fc 7 1/fc 27/fc 7 1/fc 28/fc 7 1/fc 210/fc 7 1/fc 211/fc 7 1/fc Noise canceler disable 0) R/W
RPOLS
EINT
Interrupt source select
RNC
Noise canceler noise eliminating time select
Note 1: Note 2:
fc: High-frequency clock [Hz] After reset, RPOLS do not change the set value in the receiving remote control signal. For setting interrupt edge and measurement data, use EINT and RMM.
Remote control receive control register 2
RXCR2 (00FE9H) 7 6 CREGA 5 4 3 RCS 2 RMCEN 1 RMM 0 (Initial value: 0000 0000)
CREGA
Setting of detect time for match with 8-bit up-counter upper 4 bits
Match detect time (Tth) 16 CREGA/RCCK [s] CREGA 0H to FH Example: CREGA 2H, RCCK fc/26 [Hz], at fc DV1CK 0 Tth 128 [ s] 0: 1: 0: 1: 00: 01: 10: 11: Stop and counter clear Start Disable Enable
16 MHz,
RCS RMCEN
8-bit up-counter start control Remote control signal preprocesser Enable/Disable Measurement mode select (invalid when EINT "10")
R/W
RMM
Refer to Table 2.10.1
Note 1: Note 2:
fc: High-frequency clock [Hz] When an interrupt source is set for rising/falling edge, low and high widths are forcibly measured separately.
Note 3:
Set CREGA (0H to FH) before EINT sets to 8-bit receive end.
Figure 2.10.2 Remote Control Receive Control Register 1, 2
88CS34-111
2003-03-25
TMP88CS34/CP34
Remote control receive counter register
RXCTR (00FEAH) 7 6 5 4 3 2 1 0 Read Only (Initial value: 0000 0000)
Remote control receive data buffer register
RXDBR (00FEBH) 7 6 5 4 3 2 1 0 Read Only (Initial value: 0000 0000)
Remote control receive status register
RXSR (00FECH) 7 6 RBCTM RBCTM OVFF SRM Receive bit counter value monitor 8-bit up-counter overflow flag Data buffer register input monitor Remote control signal monitor after passing through noise canceler *: Don't care 0: 1: 0: 1: No overflow Overflow Upper 4 bits of 8-bit up-counter Upper 4 bits of 8-bit up-counter CREGA CREGA 5 4 3 2 OVFF 1 SRM 0 RNCM Read Only (Initial value: 0000 *000)
Read only
RNCM Note 1:
Figure 2.10.3 Remote Control Receive Counter Register, Data Buffer Register, Status Register
88CS34-112
2003-03-25
TMP88CS34/CP34
Table 2.10.1 Combination of Interrupt Source and Measurement Mode
RPOLS EINT RMM 00 00 10 11 01 0 01 10 11 10 00 11 10 00 00 10 11 01 1 01 10 11 10 00 11 10 Receive end Receive end Interrupt source Measurement mode
88CS34-113
2003-03-25
TMP88CS34/CP34 2.10.3 Noise Elimination Time Setting
The remote control receive circuit has a noise canceler. By setting RNC in RXCR1, input signals shorter than the fixed time can be eliminated as noise. Table 2.10.2 Noise Elimination Time Setting (fc RNC
000 001 010 011 100 101 110 111
16 MHz)
Minimum signal pulse width
(25 5)/fc (28 5)/fc (29 5)/fc (210 5)/fc (211 5)/fc (213 5)/fc (214 5)/fc (2.31 s) (16.31 s) (32.31 s) (64.31 s) (128.3 s) (512.3 s) (1.024 ms)
Maximum noise width to be eliminated
(22 (25 (26 (27 (28 (210 (211 7 7 7 7 7 7 7 1)/fc 1)/fc 1)/fc 1)/fc 1)/fc 1)/fc 1)/fc (1.69 s) (13.88 s) (27.88 s) (55.88 s) (111.9 s) (447.9 s) (895.9 s)
2.10.4
Operation
(1) Interrupts at rising, falling, or rising/falling edge, and measurement modes First set EINT and RMM. Next, set RCS to "1"; the 8-bit up-counter is counted up by the internal clock. After measurement, the 8-bit up-counter value is saved in RXCTR. Then, the 8-bit up-counter is cleared, an INT3 request is generated, and the 8-bit up-counter resumes counting. If the 8-bit up-counter overflows (FFH) before measurement is completed, an INT3 request is generated and the overflow flag (OVFF) is set to "1". Then, the 8-bit up-counter is cleared. An overflow can be detected by reading OVFF by the interrupt processing. To restart the 8-bit up-counter, set RCS to "1". Setting RCS to "1" zero-clears OVFF.
88CS34-114
2003-03-25
RNCM
RCCK
INT3 request
I 3I 2I 1
8-bit up-counter value I
m 2m 1 n 2n
1 I (a) Low width measurement
2
3
m
1
2
3
1
n n
1
2
3
RXCTR
8-bit up-counter value
I 3I 2I 1
I I
1
2
3
4
5
6
7
8
m
4m
3m
2m
1
m m
Figure 2.10.4 Rising Edge Interrupt Timing Chart (RPOLS
88CS34-115
(b) Rising edge cycle measurement
I 3I 2I 1
1
2
3
RXCTR
8-bit up-counter value I
m
1
2
3
2m
1
m m
1
2
3
n
2n
1
n
1
2
3
RXCTR
0)
(c) High width measurement
TMP88CS34/CP34
2003-03-25
RNCM
RCCK
INT3 request
I 3I 2I 1
8-bit up-counter value I
m 2m 1 n
1 I (a) High width measurement
2
3
m
1
2
3
2n
1
n n
1
2
3
RXCTR
8-bit up-counter value
I 3I 2I 1
I I
1
2
3
4
5
6
7
8
m
4m
3m
2m
1
m m
Figure 2.10.5 Falling Edge Interrupt Timing Chart (RPOLS
88CS34-116
(b) Falling edge cycle measurement
I 3I 2I 1
1
2
3
RXCTR
8-bit up-counter value I 1 2 3
m
2m
1
m m
1
2
3
n
2n
1
n
1
2
3
RXCTR
0)
(c) Low width measurement
TMP88CS34/CP34
2003-03-25
RNCM
RCCK
INT3 request
I 3I 2I 1
8-bit up-counter value I
m 2m 1
1 I m
2
3
m
1
2
3
n
2n
1
n n
1
2
3
Figure 2.10.6 Rising/Falling Edge Interrupt Timing Chart
88CS34-117
RXCTR
(a) High and low width measurement
TMP88CS34/CP34
2003-03-25
TMP88CS34/CP34
(2) 8-bit receive end interrupts and measurement modes By determining one-cycle remote control signal as one-bit data set to "0" or one-pulse width remote control signal as one-bit data set to "1", an INT3 request is generated after 8-bit data is received. When "0" is determined, this means the upper four bits in the 8-bit up-counter have not reached the CREGA value. When "1" is determined, this means the upper four bits in the 8-bit up-counter have reached or exceeded the CREGA value. The 8-bit up-counter value is saved in RXCTR after one bit is determined. The determined data is saved, bit by bit, in RXDBR at the rising edge of the remote control signal (when RPOLS 1, falling edge). The number of bits saved in RXDBR is counted by the receive bit counter and saved in RBCTM. RBCTM is set to "0001B" at the rising edge of the input (when RPOLS 1, falling edge) after the INT3 request is generated.
RNCM
RCCK 8-bit up-counter value RCS OVFF Receive bit counter value* RBCTM* INT3 request n n 1 1 n n FE FF 1 Set to "1" by command
Note:
*: Valid only when 8 bits are received.
Figure 2.10.7 Overflow Interrupt Timing Chart
88CS34-118
2003-03-25
8-bit receive end interrupt setting
RNCM
Receive bit counter value 1 6 7
8
INT3 request
CREGA
1
Figure 2.10.8 8-Bit Receive End Interrupt Timing Chart (RPOLS
01 02 03 04 05 06 07 01 02 0 07
88CS34-119
8-bit up-counter value
01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11
01 02
SRM
1
RXDBR
80H [Application] Low width measurement (a) Rising Edge cycle measurement
0)
TMP88CS34/CP34
2003-03-25
TMP88CS34/CP34
Table 2.10.3 Count Clock for Remote Control Preprocessor Circuit (at fc Count clock (RCCK)
00 01 10 11
16 MHz)
Resolution [ s]
4 16 64 256
Maximum setting time [ms]
1.024 4.096 16.38 65.53
88CS34-120
2003-03-25
TMP88CS34/CP34
2.11 8-Bit AD Converter (ADC)
The TMP88CS34/CP34 has a 8-bit successive approximation type AD converter. Figure 2.11.1 shows the circuit configuration of the AD converter. The AD converter includes control registers ADCCRA and ADCCRB, conversion result registers ADCDR1 and ADCDR2, a DA converter, a sample hold circuit, a comparator, and sequential transducer circuit. To use P5 and P6 as analog inputs, clear the output latch for P5 and P6 to "0". Also, clear the input/output control registers (P5CR1 and P6CR) to "0". P63 to P61 output "0" after a reset. When these dual-function pins are used as ports, be sure to set ORP6S2 to "1".
2.11.1
Configuration
VDD
DA converter
VSS
Analog input multiplexer AIN0 AIN1 A B Y
Sample hold circuit ADS
Reference voltage
8 Analog comparator
AIN4 AIN5
E F
S
EN
SAIN AINDS
3 Shift clock Control circuit
Successive approximate circuit
EN 6 ADRS P5CR, P6CR
P5, P6 port input/output control register
INTADC
AD8TRG External trigger signal
2 AMD
3 EOCF ACK ADCCRB ADBF
8
ADCCRA
ADCDR1, ADCDR2
AD conversion result register
AD converter control register
Figure 2.11.1 AD Converter (ADC)
2.11.2
Control Register
The following register are used foe AD converter. AD converter control register 1 (ADCCRA) AD converter control register 2 (ADCCRB) AD conversion result register (ADCDR1/ADCDR2)
(1) AD converter control register 1 (ADCCRA) ADCCRA control AD conversion start, AD operation mode select, analog input control and analog input channel select. (2) AD converter control register 2 (ADCCRB) ADCCRB control AD conversion time select. (3) AD conversion result register (ADCDR1) AD conversion result is stored after end of conversion. (4) AD conversion result register (ADCDR2) For monitoring status of conversion. Figure 2.11.2 and Figure 2.11.3 show AD converter control register.
88CS34-121
2003-03-25
TMP88CS34/CP34
AD Converter Control Register 1 ADCCRA 7 6 5 (0000EH) ADRS AMD
4 AINDS
3 "0"
2
1 SAIN
0 (Initial value: 0001 0000)
ADRS
AD conversion start
AMD
AD Operating mode select
AINDS
Analog input control
SAIN
Analog input channel select
The ADRS bit is automatically cleared after starting AD conversion. During AD conversion, setting ADRS to "1" initializes the ADRS bit and resets conversion. 0: 1: AD conversion restart 00: STOP mode 01: Software start mode 10: Trigger start mode 11: reserved 0: Analog input enable 1: Analog input disable 000: Selects AIN0 001: Selects AIN1 010: Selects AIN2 011: Selects AIN3 100: Selects AIN4 101: Selects AIN5 110: 111:
R/W
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6:
Select analog input when AD converter stops. When the analog input is all use disabling, the AINDS should be set to "1". During conversion, do not perform output instruction to maintain a precision for all of the pins. And port near to analog input, do not input intense signaling of change. The ADRS is automatically cleared to "0" after starting conversion. Always set bit 3 in ADCCRA to "0". Do not set ADRS (bit 7 in ADCCRA) to "1" during AD conversion. Re-set it after confirming with EOCF (bit 5 in ADCDR2) that the conversion is completed or after generating an interrupt signal (INTADC) (by the interrupt processing routine or the like).
Note 7
In the trigger mode, the system does not accept the second and subsequent triggers after accepting the first trigger for starting AD conversion. To restart AD conversion by a trigger, set AMD (bits 6 and 5 in ADCCRA) to "00" and then put the system in trigger start mode again (with AMD "10").
Note 8:
When the system enters STOP mode, AD converter control register 1 (ADCCRA) is initialized.
Re-set this register after the system reenters NORMAL mode. AD Converter Control Register 2 7 6 5 4 3 2 1 0 ADCCRB (0000FH) "0" "1" ACK 000 001 010 ACK AD conversion time select 011 100 101 110 111 Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Do not use setting except the above list. Set conversion time by analog reference voltage (VDD) as follows. VDD 4.5 to 5.5 V (15.6 or more) Always set bit 0 and bit 5 in ADCCRB to "0" and set bit 4 in ADCCRB to "1". When a read instruction for ADCCRB, bit 6 to 7 in ADCCRB read in as undefined data. fc: High-frequency clock [Hz] When the system enters STOP mode, AD converter control register 2 (ADCCRA) is initialized. Re-set this register after the system reenters NORMAL mode. 156/fc [s] 312/fc [s] 624/fc [s] 1248/fc [s] 19.5 39.0 78.0 Reserved 19.5 39.0 78.0 39 78 156 39 78 156 R/W Reserved ACK "0" (Initial value: **0* 000*)
Conversion DV1CK 0 DV1CK 1 time fc 16 MHz fc 8 MHz fc 16 MHz fc 8 MHz
Figure 2.11.2 AD Converter Control Register
88CS34-122
2003-03-25
TMP88CS34/CP34
AD Conversion Result Register 7 6 ADCDR1 (00031H) ADCDR2 (00032H) AD07 7 AD06 6
5 AD05 5 EOCF
4 AD04 4 ADBF
3 AD03 3
2 AD02 2
1 AD01 1
0 AD00 0 (Initial value: **00 ****) (Initial value: 0000 0000)
EOCF ADBF Note 1:
AD conversion end flag AD conversion busy flag
0: 1: 0: 1:
Under conversion or Before conversion End of conversion During stop of AD conversion During AD conversion
Read only
The EOCF is cleared to "0" when reading the ADCDR1. Therefore, the AD conversion result should be read to ADCDR1 more first than ADCDR2.
Note 2:
ADBF is set to "1" by starting AD conversion and cleared to "0" by end of AD conversion. Additionally, ADBF is cleared to "0" by setting AMD "00" in ADCCR2 or entering to the STOP mode.
Note 3:
If the pin is used as an analog input pin, reset the DGINE register to "0" to disable all inputs other than analog inputs.
Figure 2.11.3 AD Converter Result Register
2.11.3
AD Converter Operation
The high side of an analog reference voltage is applied to VDD, and the low side is applied to VSS pin. Dividing a reference voltage between VDD and VSS to the voltage corresponding to a bit by a rudder resistance and comparing it with the analog input voltage converts the AD. Table 2.11.1 AD Converter Operation mode Mode
AD converter disable mode Software start mode Trigger start mode
Function
AD converter stop mode. This mode is always used to change modes. Single AD conversion of 1 channel which specifies input. Single AD conversion of 1 channel which specifies input (AD8TRG) from Key-On-Wake-Up circuit as a trigger.
2.11.4
Interrupt
Interrupt request signal occur at the timing when the EOCF bit is set to "1".
88CS34-123
2003-03-25
TMP88CS34/CP34 2.11.5 AD Converter Operation Modes
When the MCU places in the STOP mode during the AD conversion, the conversion is stopped and the ADCDR2 content becomes indefinite. After returning from the STOP mode, the EOCF and INTADC does not occur. Therefore, the AD conversion must be restarted after returning from the STOP mode.
ADS ADCDR2 Invalid Result Invalid Invalid Result
EOCF Processing Read Start Read Start Start
Figure 2.11.4 AD Conversion Timing Chart (1) AD conversion in STOP mode When the AD converter stop mode is specified during AD conversion, the AD conversion is stopped immediately. The AD conversion is not implemented, so the undefined value is not written to the AD conversion result register. The AD conversion start commands which occur is the AD converter stop mode are ignored. This mode is automatically selected by reset. This mode is used to change the AD converter operation mode. (2) Single mode When the AMD (bit 6, 5 to in ADCCRA) set to "01", the AD conversion signal mode. This mode does AD conversion of single channel, and conversion result is stored in ADCDR1. The EOCF (bit 5 in ADCDR2) is set to "1" at end of one conversion, and an intcrrupt request signal occurs. The EOCF is cleared to "0" by reading the AD conversion registers. But when the AD conversion is restarted before the ADCDR is read, the EOCF is cleared to "0" and the last AD conversion result is maintained till next conversion end. Do not set ADRS (bit 7 in ADCCRA) during AD conversion. Again set it after confirming with EOCF (bit 5 in ADCDR2) that the conversion is completed or after generating an interrupt signal (INTADC) (by the interrupt processing routine or the like).
ADS ADCDR2 EOCF ADBF Conversion time (Reference to ADCCRB register) Start Read Invalid AD conversion result
Figure 2.11.5 Single Mode
88CS34-124
2003-03-25
TMP88CS34/CP34
Example: The AD conversion starts after 19.5 s (at fc 16 MHz) and AIN4 pin are selected as the conversion time and the analog input channel. Confirming the EOCF, the converted value is read out, and the 8 bits data is stored to address 009EH in RAM. The operation mode is a signal mode. ; AIN SELECT LD (P5), 00000000B LD (P5CR1), 00000000B LD (P6), 00000000B LD (P6CR), 00000000B LD (ADCCRA), 00100100B ; Selects AIN4, Selects the software start mode LD (ADCCRB), 00011000B ; Selects the conversion time and the operation mode. ; AD CONVERT START SET (ADCCRA) . 7 SLOOP: TEST (ADCCR2) . 5 JRS T, SLOOP ; RESULT DATA READ LD (9EH), (ADCDR1) (3) Trigger start mode The AD conversion of a specified single channel is executed when input (AD8TRG) from Key-On-Wake-Up circuit is set as trigger, the conversion result is stored in the ADCDR1. The EOCF (bit 5 in ADCDR2) is set to "1" at end of one conversion, and an interrupt request signal occurs. It needs to be set the STOP mode by bit 5 to 6 in ADCCRA before the AD conversion is executed again. ; ; ADRS EOCF 1 1
2.11.6
Analog Input Voltage and AD Conversion Result
The analog input voltage is corresponded to the 8-bit digital value converted by the AD as shown in Figure 2.11.6.
AD Conversion result FFH
FEH
FDH
03H
02H
01H
0
1
2
3
253 Analog input voltage
254
255
256
VDD
VSS
256
Figure 2.11.6 Analog Input Voltage and AD Conversion Result (typ.)
88CS34-125
2003-03-25
TMP88CS34/CP34 2.11.7 STOP Modes during AD Conversion
When standby mode (STOP mode) is entered forcibly during AD conversion, the AD convert operation is suspended and the AD converter is initialized. (ADCCRA and ADCCRB are initialized to initial value.) Also, the conversion result is indeterminate. (Conversion results up to the previous operation are cleared, so be sure to read the conversion results before entering standby mode.) When restored from standby mode, AD conversion is not automatically restarted, so it is necessary to restart AD conversion after setting ADCCRA and ADCCRB. Note that since the analog reference voltage is automatically disconnected, there is no possibility of current flowing into the analog reference voltage.
2.11.8
Notice of AD converter
Voltage range of analog input (AIN0 to AIN5) must be forced from VSS to VDD. If input voltage of which out of range is forced to analog input pin, AD conversion result to unknown. Also, this cause other analog input pin unstable.
(1) Analog input voltage range
(2) I/O port with analog input Analog input pins (AIN0 to AIN5) are also I/O port. During AD conversion using any analog input pin, don't operate other I/O port with analog input. Because, AD accuracy would be worse. Also, other electrically swinging port without analog input may cause noise to near analog input pin. (3) Reduce to noise Figure 2.11.7 is shown as internal equivalent circuit of analog input pin. Increasing output impedance of analog input supply, cause noise or other non-good condition. Therefore, output impedance of analog input supply must be less than 5k . And we recommend to connect capacitance to analog input pin.
AINx Analog input supply impedance 5 k (max.)
Internal resistance R 5 k (typ.) Internal Capacitance C 22 pF (typ.)
Analog converter
DA converter
Figure 2.11.7 Analog Input Equivalent Circuit and Analog Input Pin
88CS34-126
2003-03-25
TMP88CS34/CP34
2.12 Key-On-Wake-Up
In this MCU the IDLE mode is also released by Low active port inputs. The low input voltage is regulated higher than the other normal ports. Therefore the ports can be enabled by analog input level.
2.12.1
Configuration
PORT P53 AIN0 AD Converter
KWU0
VIL
VDD
0.65 AD8TRG
KWU1
PORT P54
AIN1 Noise reject circuit
KWU2
PORT P55
AIN2
KWU3
PORT P56
AIN3 INTKWU
KWU4
PORT P60
AIN4
KWU5
PORT P61 AIN5
INTAD EN
*
IDLE5 IDLE4 IDLE3 IDLE2 IDLE1 IDLE0 EN EN EN EN EN EN
*
*
IDLE5 IDLE4 IDLE3 IDLE2 IDLE1 IDLE0 IN IN IN IN IN IN
IDLECR (00FD0H)
IDLEIN (00FD0H)
Figure 2.12.1 Key-On-Wake-Up Control Circuit
2.12.2
Control
P53 to P56 and P60, P61 ports can be controlled by IDLE control register (IDLECR). It can be configured as enable/disable in one-bit unit. When those pins are used by IDLE mode release, those pins must be set input mode (P5CR1, P5, P6CR, P6, ADCCRA). IDLE mode is controlled by system control register 2 (SYSCR2) and maskable interrupts. After the individual enable flag (EF5) is set to "1", the IDLE mode must starts. When enabled port input generates INTKWU interrupt, the IDLE mode is released. Low level input voltage in those ports is regulated to less than VDD 0.65 (V). IDLE port monitorring register (IDLEIN) can be used to check state of ports. INTADEN can enable to generate AD8TRG, which is used as trigger of AD converter trigger start mode. Noise reject circuit eliminate noise, which is less than 24 s period.
88CS34-127
2003-03-25
TMP88CS34/CP34
IDLE control register
IDLECR (00FD0H) 7 INTAD EN INTADEN IDLE5EN IDLE4EN IDLE3EN IDLE2EN IDLE1EN IDLE0EN Note : 6 * 5 IDLE5 EN 4 IDLE4 EN 3 IDLE3 EN 2 IDLE2 EN 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 1 IDLE1 EN Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Write only 0 IDLE0 EN (Initial value: 0*00 0000)
Generation of AD8TRG Release IDLE mode by KWU 5 Release IDLE mode by KWU 4 Release IDLE mode by KWU 3 Release IDLE mode by KWU 2 Release IDLE mode by KWU1 Release IDLE mode by KWU 0
*: Don't care
IDLE port monitorring register
IDLEIN (00FD0H) 7 * 6 * 5 IDLE5 IN 4 IDLE4 IN 3 IDLE3 IN 2 IDLE2 IN 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 1 IDLE1 IN "0" detect "1" detect "0" detect "1" detect "0" detect "1" detect "0" detect "1" detect "0" detect "1" detect "0" detect "1" detect Read only 0 IDLE0 IN (Initial value: **00 0000)
IDLE5IN IDLE4IN IDLE3IN IDLE2IN IDLE1IN IDLE0IN Note :
Input level of KWU 5 Input level of KWU 4 Input level of KWU 3 Input level of KWU 2 Input level of KWU1 Input level of KWU 0
*: Don't care
Figure 2.12.2 Key-On-Wake-Up Control Register
88CS34-128
2003-03-25
TMP88CS34/CP34
2.13 Pulse Width Modulation Circuit Output
The TMP88CS34/CP34 has four 12-bit resolution PWM output channels including two 14-bit resolution selectable. DA converter output can easily be obtained by connecting an external low-pass filter. PWM outputs are multiplexed with general purpose I/O ports as; P40 ( PWM0 ) to P43 ( PWM3 ). PWM output is negative logic. When these ports are used PWM outputs, the corresponding bits of P4, P5 output latches and input/output control latches should be set to "1". In STOP mode, PWM output pin keeps high-level. When operation mode is changed from STOP mode to NORMAL mode, PWM control register (PWMCR1A, PWMCR1B) are initialized.
2.13.1
Configuration
12-Bit Resolution PWM output
Internal counter (2) 14 13 12 11 10 9 Internal counter (1) 87654321 clock (fc/2 or fc/22)
PWM0 PWM1 PWM2 PWM3
Additional pulse generate circuit 13
PWM Data Latch
Compare circuit
ALL "0" 8 7
PWM Data Latch
S R
0
5
0
7
0
Transfer Buffer (the lower)
Transfer Buffer (the upper)
7 PWMDBR1
0
2
0
PWMCR1B
PWM Control Register 1B
0 PWMCR1A PWM Control Register 1A
6
Figure 2.13.1 PWM Output Circuit
88CS34-129
2003-03-25
TMP88CS34/CP34 2.13.2 PWM Output Wave Form
(1) PWM0 to PWM1 Outputs
PWM0 and PWM1 output can be selected 12-bit or 14-bit resolution PWM outputs.
1.
12-bit Resolution PWM Output When these are used as 12-bit PWM output, one period is TM 213/fc [s] (When DV1CK 0) and TM 214/fc [s] (When DV1CK 1) and sub-period is TS TM/16. The lower 8-bit of the PWM data latch controls the low level pulse width with a cycle of TS. The lower 8-bit of the PWM data latch is n (n 1 to 255), the low level pulse width with a cycle becomes n x t0 [s] (t0 2/fc [s] when DV1CK 0, t0 4/fc [s] when DV1CK 1). The upper 4-bit of the PWM data latch controls a position to output the additional pulses. When the upper 4-bit of the PWM data latch is m, the additional pulses are generated in each of m periods out of 16 periods contained in a TM period. The relationship between the 4-bit data and the position of TS period where the additional pulses are generated is shown in Table 2.13.1. Table 2.13.1 The addition pulse (12 bit mode)
Bit position of the lower 4 bits of PWMDRxH Bit 11 Bit 10 0 0 0 1 0 Bit 9 0 0 1 0 0 Bit 8 0 1 0 0 0 Relative position of TS in TM period where the additional pulse is generated. (Number of TS (I) is listed) No additional pulse 8 4, 12 2, 6, 10, 14 1, 3, 5, 7, 9, 11, 13, 15
a) b) c) d) e) Note 1: Note 2:
0 0 0 0 1
The bit positions of a) to e) can be combined. If the low order eight bits for the PWM data latch are set to "FFH", be sure to set the high order four bits for this latch to "00H".
2.
14-bit Resolution PWM Output When these are used as 14-bit PWM output, one period is TM 215/fc [s] (When DV1CK 0) and TM 216/fc [s] (When DV1CK 1) and sub-period is TS TM/64. The lower 8-bit of the PWM data latch controls the low level pulse width with a cycle of TS. The lower 8-bit of the PWM data latch is n (n 1 to 255), the low level pulse width with a cycle becomes n x t0 [s] (t0 2/fc [s] when DV1CK 0, t0 4/fc [s] when DV1CK 1). The upper 6-bit of the PWM data latch controls a position to output the additional pulses. When the upper 6-bit of the PWM data latch is m, the additional pulses are generated in each of m periods out of 64 periods contained in a TM period. The relationship between the 6-bit data and the position of TS period where the additional pulses are generated is shown in Table 2.13.2. Table 2.13.2 The addition pulse (14 bit mode)
Bit position of the lower 6 bits of PWMDRxH Bit 13 Bit 12 0 0 0 0 0 1 0 Bit 11 0 0 0 0 1 0 0 Bit 10 0 0 0 1 0 0 0 Bit 9 0 0 1 0 0 0 0 Bit 8 0 1 0 0 0 0 0 Relative position of TS in TM period where the additional pulse is generated. (Number of TS (I) is listed) No additional pulse 32 16, 48 8, 24, 40, 56 4, 12, 20, 28, 36, 44, 52, 60 2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31, 33, 35, 37, 39, 41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 61, 63
a) b) c) d) e) f) g) Note 1: Note 2:
0 0 0 0 0 0 1
The bit positions of a) to g) can be combined. If the low order eight bits for the PWM data latch are set to "FFH", be sure to set the high order six bits for this latch to "00H".
88CS34-130
2003-03-25
TMP88CS34/CP34
(2) PWM2 to PWM3 Outputs
PWM2 and PWM3 output are 12-bit resolution PWM outputs.
One period is TM 213/fc [s] (When DV1CK and sub-period is TS TM/16.
0) and TM 214/fc [s] (When DV1CK
1)
The lower 8-bit of the PWM data latch controls the low level pulse width with a cycle of TS. The lower 8-bit of the PWM data latch is n (n 1 to 255), the low level pulse width with a cycle becomes n x t0 [s] (t0 2/fc [s] when DV1CK 0, t0 4/fc [s] when DV1CK 1). The upper 4-bit of the PWM data latch controls a position to output the additional pulses. When the upper 4-bit of the PWM data latch is m, the additional pulses are generated in each of m periods out of 16 periods contained in a TM period. The relationship between the 4-bit data and the position of TS period where the additional pulses are generated is shown in Table 2.13.1.
14-bit resolution PWM mode: the additional pulse Ts (0) and Ts (63)
TM TS (0) n
PWM0
64 TS TS (63) t0 t0
TS (1)
t0
to
PWM1
Pulse width
n
t0
Pulse width
(n
1) t0
12-bit resolution PWM mode: the additional pulse Ts (0) and Ts (15)
TS (0) n
PWM2
TS (1) t0
TS (15) t0
t0
to
PWM3
Pulse width
n
t0
Pulse width
(n
1) t0
Note 1: Note 2:
If the pulse width is set to "00H", PWM will not operate. Its output will remain high. If the pulse width is set to "FFH", settings for additional pulses cannot be made. Be sure to set the pulse width to "00H".
Figure 2.13.2 PWM Output Wave Form
88CS34-131
2003-03-25
TMP88CS34/CP34 2.13.3 Control
PWM output is controlled by PWM Control Register (PWMCR1A, PWMCR1B) and PWM Data Buffer Register (PWMDBR1). PWM Control Register 1A
7 PWMCR1A (00028H) 6 5 4 3 2 ABORT1 START3 START2 START1 START0 Abort PWM operation of channel 3 to 0 Start channel 3 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 1 0 RESOLUTION 1 0 (Initial value: *000 0000)
ABORT1 START3
Operation PWM Abort (PWM outputs are fixed to a high-level.) Stop PWM3 Start PWM3 Stop PWM2 Start PWM2 Stop PWM1 Start PWM1 Stop PWM0 Start PWM0 14-bit resolution 12-bit resolution 14-bit resolution 12-bit resolution Write only
START2 START1
Start channel 2 Start channel 1
START0
Start channel 0
RESOLUTION1 Select channel 1 resolution RESOLUTION2 Select channel 0 resolution Note 1: Note 2 Note 3: *: Don't care
After set the ABORT1 to "1", the ABORT1 is cleared to "0" automatically. PWMCR1A is write-only register and cannot be used with any of the read-modify-write instructions such as SET, CLR, etc.
PWM Control Register 1B
7 PWMCR1B (00029H) 6 5 4 3 2 1 PWMCHS1 0 PWMHL (Initial value: **** *000)
PWMCHS1
Select the PWM data latch of 12-bit PWM channels Select upper or lower data transfer buffer (PWMDBR1)
00: 01: 10: 11: 0: 1:
Channel 0 Channel 1 Channel 2 Channel 3 Lower 8-bit Upper 4-bit or 6-bit
Write only
PWMHL Note 1: Note 2:
*: Don't care PWMCR1B is write-only register and cannot be used with any of the read-modify-write instructions such as SET, CLR, etc.
PWM Data Buffer Register 1
7 PWMDBR1 (0002AH) Note 1: 6 5 4 3 2 1 0 Write only (Initial value: 0000 0000)
PWMDBR1 is write-only register and cannot be used with any of the read-modify-write instructions such as SET, CLR, etc.
Note 2:
When operation mode is changed from STOP mode to NORMAL mode, PWMCR1A, PWMCR1B are initialized.
Figure 2.13.3 PWM Control Register 1A/1B and PWM Data Buffer Register 1
88CS34-132
2003-03-25
TMP88CS34/CP34
Binary Counter Control Register
7 CGCR (00030H) "0" 6 "0" 5 DV1CK 4 "0" 3 "0" 2 "0" 0: 1: fc/4 fc/8 1 "0" 0 "0" (Initial value: 0000 0000)
DV1CK Note 1: Note 2:
Select of input clock to 1st divider
R/W
*: Don't care The all bits except DV1CK are cleared to "0".
Figure 2.13.4 DIVIDER Control Register (1) Internal Counter The internal counter of PWM outputs is a free running counter. The all bits of counter are set to "1" and are not counted up at one of the following conditions. 1. 2. 3. 4. 5. During reset The operation mode is changed to STOP mode. Setting ABORT1 to "1". The START3 to 0 are "0" in 12-bit PWM outputs. The lower 8-bit of PWM data latch in 12-bit PWM outputs is "00H". The PWM data latch in 7-bit PWM outputs is "00H".
(2) Outputs control and Programming of PWM data The PWM outputs are fixed to a high-level immediately when the ABORT1 is set to "1". The PWM outputs starts the operation when the STARTx (x: 0 to 3) is set to "1". The data from the transfer buffer to a PWM data latch is transferred when the all bits of internal counter are set to "1". Therefore, the data is transferred to a PWM data latch immediately when the internal counter is initialized. And the data is transferred to a PWM data latch at the beginning of the next cycle when all bits of the internal counter are not set to "1". The sequence of writing the output data to PWM data latches is shown as follows; 1.
PWM0 to PWM1
a. b. c. d. e.
Write the channel number of PWM data latch to PWMCHS1 (bit 2 and 1 in PWMCR1B) and clear PWMHL (bit 0 in PWMCR1B) to "0". Write the lower 8-bit PWM output data to PWMDBR1. Write the channel number of PWM data latch to PWMCHS1 and set PWMHL to "1". Write the upper 4-bit or 6-bit PWM output data to PWMDBR1. Select the resolution of PWM output to RESOLUTIONx (x: 0, 1) (bit 0 and 1 in PWMCR1A) and set STARTx (x: 0, 1) (bit 2 and 3 in PWMCR1B) to "1". PWM output data must be write to PWMDBR1 in the order of the lower 8-bit PWM output data, the upper 4-bit (or 6-bit) PWM output data. If the upper 4-bit (or 6-bit) PWM output data is write to PWMDBR1, the lower 8-bit PWM output data is not changed (Except when lower 8-bit PWM output data is "00H".).
Note:
88CS34-133
2003-03-25
TMP88CS34/CP34
2.
PWM2 to PWM3
a. b. c. d. e.
Write the channel number of PWM data latch to PWMCHS1 and clear PWMHL to "0". Write the lower 8-bit PWM output data to PWMDBR1. Write the channel number of PWM data latch to PWMCHS1 and set PWMHL to "1". Write the upper 4-bit PWM output data to PWMDBR1. Set STARTx (x: 2, 3) to "1".
1) Data transfer timing and STOP/ABORT timing (X: 0 to 3) TM TS
PWMx
TM TS
m
t0 Writing PWMDBR1 (data m to n)
n
t0
TS
PWMx
STARTx 0 or The lower 8-bit of PWM data latch TS
PWMx
00H
ABORT1 1 or STOP mode 2) Restart timing when operating for 1ch or more TM
PWM0
TM
PWM1
Restarting PWM1 3) Restart timing after all channels stop TM
Restarts after one cycle.
TM
Start command
Figure 2.13.5 Wave form of PWM0 to PWM3 Note: PWM output data must be write to PWMDBR1 in the order of the lower 8-bit PWM output data, the upper 4-bit (or 6-bit) PWM output data. If the upper 4-bit (or 6-bit) PWM output data is write to PWMDBR1, the lower 8-bit PWM output data is not changed (Except when lower 8-bit PWM output data is "00H".).
88CS34-134
2003-03-25
TMP88CS34/CP34
Example: At fc 16 MHz, DV1CK 0
PWM0 pin outputs a 14-bit resolution PWM wave form with a low-level of 32 s width and no additional pulse. PWM1 pin outputs a 12-bit resolution PWM wave form with a low-level of 16 s width and no additional pulse.
LD (CGCR), 00H LD LD LD LD LD LD LD LD LD (PWMCR1B),00H (PWMDBR1),80H (PWMCR1B),01H (PWMDBR1),00H (PWMCR1B),02H (PWMDBR1),40H (PWMCR1B),03H (PWMDBR1),01H (PWMCR1A),0DH
; DV1CK ; ; ; ; ; ; ; ; ;
0
Select the lower 8-bit of PWM0 output data latch 32 s 4/fc 80H Select the upper 6-bit of PWM0 output data latch No additional pulse 00H Select the lower 8-bit of PWM0 output data latch 16 s 4/fc 40H Select the upper 4-bit of PWM0 output data latch Additional pulse (Ts (8)) 01H Start PWM0 and PWM1 , PWM0 : 14-bit resolution, PWM1 : 12-bit resolution
88CS34-135
2003-03-25
TMP88CS34/CP34
2.14 On-Screen Display (OSD) Circuit
The TMP88CS34/CP34 features a built-in on-screen display circuit used to display characters and symbols on the TV screen. There are 383 characters of mono font and 96 characters of color font (447 characters of mono font and 64 characters of color font) and any characters can be displayed in an area of 32 columns 12 lines (include 2 columns for solid space). With an OSD interrupt, additional lines can be displayed. OSD circuit functions are as follows : (1) Number of character fonts : mono font 383 and color font 96 mono font 447 and color font 64 (2) Number of display characters (3) Composition of character (4) Character sizes : 384 (32 columns : horizontal 16 12 lines). vertical 18 dots
: 3 kinds for large, middle and small characters (Selectable line by line)
(5) Character ornamentation function Fringing function : mono font Smoothing function : mono font Slant function (Italics) : mono font Blinking function Underline (6) Solid space (7) Area plane function (8) Full-raster blanking function (9) Display colors Character colors Fringe color Background color Area plane color Raster color (10) Display position (11) Window function (13) 27 colors display function (14) Color palette (15) PAL100/NTSC120 display Note: The function of the OSD circuit don't meet the requirements of on-screen display functions of closed caption decoders based on FCC standards. : : : : : 8 or 27 colors (selectable character by character) 8 or 27 colors (selectable page by page) 8 or 27 colors (selectable page by page) 8 or 27 colors (selectable each of 2 planes) 8 or 27 colors (selectable page by page) : 256 horizontal steps and 625 vertical steps for code plane : 512 horizontal steps and 625 vertical steps for Area plane : 625 vertical steps : 2 planes
(12) Half transparency output function
88CS34-136
2003-03-25
TMP88CS34/CP34
The TMP88CS34/CP34 outputs OSD through 3 planes; code, area, and raster. 3 planes function independently. In addition, they are displayed simultaneously. There is the priority among these 3 planes, so they are displayed on a screen according to the priority. These 3 planes have the priority such as Code Area Raster. 1. Code plane OSD character is displayed on the code plane. The code plane consists of 32 characters have the priority such as code 1 code 2 1 row and a total of 12 planes. The 12 planes code 11 code 12.
On the code plane, characters of 16 18 dots is displayed. These fonts are called characters, and read from character ROM and display memory through the character code on the display memory. 2. Area plane The area on a screen is displayed on the area plane. The area plane can display 2 square areas of any size by specifying coordinates. The 2 planes have the priority such as area plane 1 area plane 2.
88CS34-137
2003-03-25
TMP88CS34/CP34 2.14.1 OSD Configuration
Shown below is the block diagram of the OSD circuit.
TLCS-870/X CPU ROM: 64 Kbytes RAM: 1.5 Kbytes Interrupt control circuit Clock generator Oscillator for OSD XIN XOUT OSC1 OSC2
OSD interrupt
LC oscillation control P70 ( HD ) Jitter elimination circuit P71 ( VD ) Horizontal position counter Horizontal position decoder Vertical position counter Vertical position decoder
OSD control I Display RAM 32 12 16 bits 6 Kbytes Y/BL Display B output G control R Output signal selecter
I Y/BL B G R To the lower row (A)
Caracter ROM 384 16 18 bits 96 16 18 3 bits 24 Kbyte (mono) 18Kbyte P57 (I)
Output timing
I Y/BL (A) B G R Intermediate-value enable signal Color palette circuit Data signal OSD control
P67 (Y/BL) P66 (B) P65 (G) P64 (R)
synchronization circuit
Figure 2.14.1 OSC Block Diamgram
2.14.2
Monochrome and Color Fonts
The TMP88CS34 can display both monochrome and color fonts. The monochrome font is intended for monochromic display. Each character in the font consists of 18 vertical 16 horizontal dots. For the color font, each display dot in each character can be specified separately for R (red), G (green), and B (blue). Each character consists of 18 vertical 16 horizontal dots. The monochrome and color fonts can be mixed on one display row.
88CS34-138
2003-03-25
TMP88CS34/CP34 2.14.3 Character ROM and Display Memory
The character ROM incorporates 383 different monochrome font character data items and 96 different color font character data items (447 different monochrome font character data items and 64 different color font character data items). Users can define font data. Each monochrome character ROM data item consists of 16 18 dots. Each monochrome font dot corresponds to one character ROM bit. A value of "1" represents a display state, and a value of "0" represents a non-display state. Each color font character ROM data item consists of 16 18 dots for red, 16 18 dots for green, and 16 18 dots for blue. Each color font dot corresponds to three character ROM bits (with each bit corresponding to red, green, or blue). The character ROM start address for each character code is calculated as listed in Table 2.14.1. Table 2.14.1 Number of Character Patterns and Character Codes Number of usable character patterns Monochrome font
383 447
(1) Character ROM
Usable character codes Monochrome font
1 to 17FH 1 to 17FH, 1C0H to 1FFH
Color font
96 64
Color font
180H to 1DFH 180H to 1BFH
Register for switching number of fonts, ROMACH (bit 4 in ORDON) 0 1
Table 2.14.2 Monochrome/Color Font Character ROM Start Address ROMACH Character ROM start address
Monochrome font (CRA 1 to 17FH) Character ROM start address CRA 40H 20000H Color font (CRA 180H to 1DFH) Character ROM start address for red CRA 40H 26000H Character ROM start address for green CRA 40H 27800H Character ROM start address for blue CRA 40H 29000H Monochrome font Character ROM start address CRA 40H 20000H (CRA 1 to 17FH) Character ROM start address CRA 40H 27000H (CRA 1C0H to 1DFH) Character ROM start address CRA 40H 28C00H (CRA 1E0H to 1EFH) Character ROM start address CRA 40H 2A400H (CRA 1F0H to 1FFH) Color font (CRA=180H to 1BFH) Character ROM start address for red CRA 40H 26000H Character ROM start address for green CRA 40H 27800H Character ROM start address for blue CRA 40H 29000H
0
1
Figure 2.14.2 (a) shows an example of configuring a character font (character code 001H) as well as monochrome font ROM addresses and the related data. Figure 2.14.2 (b) shows a character ROM dump list for this character font (character code 001H).
Figure 2.14.3 (a) shows an example of configuring a character font (character code 180H) as well as color font ROM addresses and the related data. Figure 2.14.4 (b) shows a character ROM dump list for this character font.
88CS34-139
2003-03-25
TMP88CS34/CP34
Note 1: A data cannot be read from character ROM by software. Note 2: When ordering a mask, load the data to character ROM at addresses 20000H to 2A7FFH. And the data in unused are of character ROM are must be specified to FFH. Note 3: Do not use character code 000H
Address Data (Hex) (Hex) 20040 3F 20041 7F 20042 E0 20043 C0 20044 00 20045 00 20046 00 20047 01 20048 03 20049 07 2004A 0E 2004B 1C 2004C 38 2004D 70 2004E FF 2004F FF 20050 00 20051 00
Bit Bit 7 6 5 4 3 2 1 07 6 5 4 3 2 1 0
Address Data (Hex) (Hex) 20060 C0 20061 E0 20062 70 20063 30 20064 30 20065 70 20066 E0 20067 C0 20068 80 20069 00 2006A 00 2006B 00 2006C 00 2006D 00 2006E F0 2006F F0 20070 00 20071 00
(Character code 001H) (a) Character font configuration of mono font
20000/ 20010/ 20020/ 20030/ 20040/ 20050/ 20060/ 20070/
00 00 00 00 3F 00 C0 00
00 00 00 00 7F 00 E0 00
00 FF 00 FF E0 FF 70 FF
00 FF 00 FF C0 FF 30 FF
00 FF 00 FF 00 FF 30 FF
00 FF 00 FF 00 FF 70 FF
00 FF 00 FF 00 FF E0 FF
00 FF 00 FF 01 FF C0 FF
00 FF 00 FF 03 FF 80 FF
00 FF 00 FF 07 FF 00 FF
00 FF 00 FF 0E FF 00 FF
00 FF 00 FF 1C FF 00 FF
00 FF 00 FF 38 FF 00 FF
00 FF 00 FF 70 FF 00 FF
00 FF 00 FF FF FF F0 FF
00 FF 00 FF FF FF F0 FF
(b) ROM dump list of mono font Note: Shaded portions indicate unused data.
Figure 2.14.2 Character Font Configuration and ROM Dump List
88CS34-140
2003-03-25
TMP88CS34/CP34
R data
Address Data (Hex) (Hex) 26000 00 26001 3F 26002 3F 26003 30 26004 30 26005 30 26006 30 26007 30 26008 3F 26009 3F 2600A 37 2600B 33 2600C 31 2600D 30 2600E 30 2600F 30 26010 30 26011 00 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 Bit 43 00 11 11 10 10 10 10 10 11 11 10 10 10 10 10 10 10 00 2 0 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 7 0 1 1 0 0 0 0 0 1 1 0 1 1 1 0 0 0 0 6 0 1 1 0 0 0 0 0 1 1 0 0 1 1 1 0 0 0 5 0 1 1 0 0 0 0 0 1 1 0 0 0 1 1 1 0 0 Bit 43 00 10 11 11 01 01 01 11 11 10 00 00 00 00 10 11 11 00 2 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Data Address (Hex) (Hex) 00 26020 F0 26021 F8 26022 1C 26023 0C 26024 0C 26025 0C 26026 1C 26027 F8 26028 F0 26029 00 2602A 80 2602B C0 2602C E0 2602D 70 2602E 38 2602F 1C 26030 00 26031
(Character code 180H) G data
Address Data (Hex) (Hex) 27800 00 27801 0F 27802 1F 27803 38 27804 30 27805 30 27806 30 27807 30 27808 30 27809 30 2780A 30 2780B 30 2780C 30 2780D 30 2780E 38 2780F 1F 27810 0F 27811 00 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 Bit 43 00 01 11 11 10 10 10 10 10 10 10 10 10 10 11 11 01 00 2 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 7 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 6 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 1 1 0 5 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 1 1 0 Bit 43 00 10 11 11 01 01 00 00 00 11 11 01 01 01 11 11 10 00 2 0 0 0 1 1 1 0 0 0 1 1 1 1 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Data Address (Hex) (Hex) 00 27820 F0 27821 F8 27822 1C 27823 0C 27824 0C 27825 00 27826 00 27827 00 27828 7C 27829 7C 2782A 0C 2782B 0C 2782C 0C 2782D 1C 2782E F8 2782F F0 27830 00 27831
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
Synthesized data used for color font display
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 5 5 7 7 7 7 7 7 7 7 7 7 7 7 5 5 0
0 5 7 7 7 7 7 7 7 7 7 7 7 7 7 7 5 0
0 7 7 2 0 0 0 1 5 4 0 0 0 0 2 3 3 0
0 7 7 0 0 0 0 1 5 4 4 0 0 0 0 3 3 0
0 7 7 0 0 0 0 1 5 4 4 4 0 0 0 3 3 0
0 7 7 0 0 0 0 1 5 4 4 4 4 0 0 3 3 0
0 7 7 0 0 0 0 1 5 4 0 4 4 4 0 3 3 0
0 7 7 0 0 0 0 1 5 6 2 0 4 4 4 3 3 0
0 7 7 1 0 0 1 1 5 6 2 0 0 4 4 7 3 0
0 6 7 7 1 1 1 5 5 7 2 0 0 0 7 7 7 0
0 0 6 7 7 7 5 4 5 3 3 3 3 3 3 7 4 0
0 0 0 6 6 6 4 4 0 3 3 3 3 3 3 0 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
(Character code 180H) B data
Address Data (Hex) (Hex) 29000 00 29001 3F 29002 3F 29003 30 29004 30 29005 30 29006 30 29007 3F 29008 3F 29009 30 2900A 30 2900B 30 2900C 30 2900D 30 2900E 30 2900F 3F 29010 3F 29011 00 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 Bit 43 00 11 11 10 10 10 10 11 11 10 10 10 10 10 10 11 11 00 2 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 1 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 7 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 6 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 5 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 Bit 43 00 00 10 11 01 01 11 10 11 11 01 01 01 01 11 11 10 00 2 0 0 0 0 1 1 1 0 0 1 1 1 1 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Data Address (Hex) (Hex) 00 29020 E0 29021 F0 29022 18 29023 0C 29024 0C 29025 1C 29026 F0 29027 F8 29028 1C 29029 0C 2902A 0C 2902B 0C 2902C 0C 2902D 1C 2902E F8 2902F F0 29030 00 29031
(Character code 180H)
0 1 2 3 4 5 6 7
: : : : : : : :
R G B Color 0 0 0 Transparent or black 0 0 1 Blue 0 1 0 Green 0 1 1 Cyan 1 0 0 Red 1 0 1 Magenta 1 1 0 Yellow 1 1 1 White
(Character code 180H)
Note 1: .
Specifying primary color outputs by color palette specification causes the ROM-specified color to be displayed.
(a) Example of configuring a color font character pattern (CRA
180H)
Figure 2.14.3 (1/2)
88CS34-141
2003-03-25
TMP88CS34/CP34
26000/ 26010/ 26020/ 26030/ 27800/ 27810/ 27820/ 27830/ 29000/ 29010/ 29020/ 29030/
00 30 00 1C 00 0F 00 F0 00 3F 00 F0
3F 00 F0 00 0F 00 F0 00 3F 00 E0 00
3F FF F8 FF 1F FF F8 FF 3F FF F0 FF
30 FF 1C FF 38 FF 1C FF 30 FF 18 FF
30 FF 0C FF 30 FF 0C FF 30 FF 0C FF
30 FF 0C FF 30 FF 0C FF 30 FF 0C FF
30 FF 0C FF 30 FF 00 FF 30 FF 1C FF
30 FF 1C FF 30 FF 00 FF 3F FF F0 FF
3F FF F8 FF 30 FF 00 FF 3F FF F8 FF
3F FF F0 FF 30 FF 7C FF 30 FF 1C FF
37 FF 00 FF 30 FF 7C FF 30 FF 0C FF
33 FF 80 FF 30 FF 0C FF 30 FF 0C FF
31 FF C0 FF 30 FF 0C FF 30 FF 0C FF
30 FF E0 FF 30 FF 0C FF 30 FF 0C FF
30 FF 70 FF 38 FF 1C FF 30 FF 1C FF
30 FF 38 FF 1F FF F8 FF 3F FF F8 FF
(b) Color font ROM dump list (CRA Note: Shading indicates data in unused areas.
180H)
Figure 2.14.4 (2/2)
88CS34-142
2003-03-25
TMP88CS34/CP34
(2) Display memory Each character of the 384 characters displayed in 32 columns 12 lines consists of 16 bits in the display memory. Five data items are written to the display memory: character code, color data, blinking specification, underline enable, and slant enable. There are two modes for writing display data to the display memory. One mode is used for writing all display data (character code, color data, blinking specification, underline enable, and slant enable) simultaneously. The other mode is used for changing either character codes or the remaining data items (color data, blinking specification, underline enable, and slant enable). How to write display data to the display memory is described in section 2.14.6.7 (1). Note: The display memory is in an unknown state at reset.
Display memory configuration Character code specification register (9 bits)............CRA8 to CRA0 Color data specification register (4 bits) ...................IDT/RDT/GDT/BDT Blinking specification register (1 bit) ........................BLF Underline enable register (1 bit)................................EUL Slant enable register (1 bit) .......................................SLNT Flag (1 bit) for specifying whether to turn on or off the character-specific background .....ECBKD
If ECHDSN
SLNT EUL
0
BLF ECBKD RDT GDT BDT CRA8 CRA7 CRA6 CRA5 CRA4 CRA3 CRA2 CRA1 CRA0
Character color Blinking specification register Underline enable register Slant enable register
Character code specification register
Flag for specifying whether to turn on or off the character-specific background
If ECHDSN
RBDT GBDT
1
BLF ECBKD RDT GDT BDT CRA8 CRA7 CRA6 CRA5 CRA4 CRA3 CRA2 CRA1 CRA0
Character color Blinking specification flag Character-specific background color of red Character-specific background color of green
Character code
Flag for specifying whether to turn on or off the character-specific background
Figure 2.14.5 Display Memory Bit Configuration
Column Line 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 000 001 002 003 004 005 006 007 008 009 00A 00B 00C 00D 00E 00F 010 011 012 013 014 015 016 017 018 019 01A 01B 01C 01D 01E 01F 020 021 022 023 024 025 026 027 028 029 02A 02B 02C 02D 02E 02F 030 031 032 033 034 035 036 037 038 039 03A 03B 03C 03D 03E 03F 040 060 080 0A0 0C0 0E0 100 120 140 160 17F
Note:
Numerals in the table indicate (hexadecimal) addresses in the display memory.
Figure 2.14.6 Display Memory Address Configuration
88CS34-143
2003-03-25
TMP88CS34/CP34
(3) Color palette The color palette can contain eight colors out of 27 colors and the display colors are specified by the color palette registers (ORCPT0-7). The color palette registers (ORCPT0-7) are assigned by the RGB setting register for each display mode (character, background, fringe,area, raster). RGB setting register values and their corresponding color palette registers RGB RGB RGB RGB 000b 010b 100b 110b ORCPT0 ORCPT2 ORCPT4 ORCPT6 RGB RGB RGB RGB 001b 011b 101b 111b ORCPT1 ORCPT3 ORCPT5 ORCPT7
Configuration of the color palette registers
Register Name Bit 7 Bit 6 Bit 5 R Bit 4 Bit 3 G Bit 2 Bit 1 B Bit 0
Address
ORCPT0
00FC6
Color palette composition register 0 CPT1MD1: OSD color select register CPT1MD1 0 (fixed) CPT0R1 CPT0R0 CPT0G1 CPT0G0 CPT0B1 CPT0B0 (x 1, 2) CPT1MD1 0: 8 color mode CPT1MD1 1: 27 color mode CPT1R1 CPT1R0 CPT1G1 CPT1G0 CPT1B1 CPT1B0 Color palette composition register 1 CPT2R1 CPT2R0 CPT2G1 CPT2G0 CPT2B1 CPT2B0 Color palette composition register 2 CPT3R1 CPT3R0 CPT3G1 CPT3G0 CPT3B1 CPT3B0 Color palette composition register 3 CPT4R1 CPT4R0 CPT4G1 CPT4G0 CPT4B1 CPT4B0 Color palette composition register 4 CPT5R1 CPT5R0 CPT5G1 CPT5G0 CPT5B1 CPT5B0 Color palette composition register 5 CPT6R1 CPT6R0 CPT6G1 CPT6G0 CPT6B1 CPT6B0 Color palette composition register 6 CPT7R1 CPT7R0 CPT7G1 CPT7G0 CPT7B1 CPT7B0 Color palette composition register 7
ORCPT1 ORCPT2 ORCPT3 ORCPT4 ORCPT5 ORCPT6 ORCPT7
00FC7 00FC8 00FC9 00FCA 00FCB 00FCC 00FCD
Color palette setting and output colors 27-color mode (CPT1MD1 1) 3-value output n 0 to 7 xR CPTnx1/CPTnx0 1/1 Bright red CPTnx1/CPTnx0 1/0 or 0/1 Dark red CPTnx1/CPTnx0 0/0 No output 8-color mode (CPT1MD1 0) 2-value output n 0 to 7 xR CPTnx1/CPTnx0 1/1 Bright red CPTnx1/CPTnx0 1/0 or 0/1 Bright red CPTnx1/CPTnx0 0/0 No output Setting the display colors The color palette registers are assigned by setting RGB data for each display mode. The display colors are then specified in the color palette registers. Setting the character color to bright red and the background color to dark blue for the code plane.
Setting character color: After setting the character code, set ORDSN (RDT 0, GDT 1, BDT 0). (Assign a color palette register.) RGB-010b corresponds to color palette register ORCPT2. To set the character color to bright red, set ORCPT2=00110000b. (Set the display color in color palette register.) Setting background color: Set background setting register ORBK (0FA5h) (RBDT 0, GBDT 0, BBDT 1). (Assign a color palette register.) RGB 001b corresponds to color palette register ORCPT1. To set the background color to dark blue, set ORCPT1 00000001b. (Set the display color in color palette register.)
xG Bright green Dark green No output xG Bright green Bright green No output
xB Bright blue Dark blue No output xB Bright blue Bright blue No output
88CS34-144
2003-03-25
TMP88CS34/CP34
(4) Color font For the color font, the display color (R, G, B) can be specified on a dot-by-dot basis. The size of the color font is 18 dots long by 16 dots wide, which is the same as the size of the normal font (mono font). A dot of the color font is comprised of three bits. Font data is combination of three bits (R, G, B) and they are arranged in the order of R (upper), G (middle), B (lower). The color palette registers are assigned by combining these three bits of data.
PONML K J I HGF EDCB A 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
PONML K J I HGF EDCB A 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
PONML K J I HGF EDCB A 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
0 1 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0
0 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0
0 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0
0 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0
0 1 1 0 0 0 0 0 1 1 0 1 1 1 0 0 0 0
0 1 1 0 0 0 0 0 1 1 0 0 1 1 1 0 0 0
0 1 1 0 0 0 0 0 1 1 0 0 0 1 1 1 0 0
0 1 1 1 0 0 0 1 1 1 0 0 0 0 1 1 1 0
0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 0
0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0
0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0
0 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0
0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 1 1 0
0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 1 1 0
0 1 1 1 0 0 0 0 0 1 1 0 0 0 1 1 1 0
0 0 1 1 1 1 0 0 0 1 1 1 1 1 1 1 0 0
0 0 0 1 1 1 0 0 0 1 1 1 1 1 1 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0
0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0
0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0
0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0
0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0
0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0
0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0
0 0 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 0
0 0 0 1 1 1 1 0 1 1 1 1 1 1 1 1 0 0
0 0 0 0 1 1 1 0 0 1 1 1 1 1 1 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R data (Upper)
G data (Middle)
B data (Lower)
PONML K J I HGF EDCB A 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 5 5 7 7 7 7 7 7 7 7 7 7 7 7 5 5 0
0 5 7 7 7 7 7 7 7 7 7 7 7 7 7 7 5 0
0 7 7 2 0 0 0 1 5 4 0 0 0 0 2 3 3 0
0 7 7 0 0 0 0 1 5 4 4 0 0 0 0 3 3 0
0 7 7 0 0 0 0 1 5 4 4 4 0 0 0 3 3 0
0 7 7 0 0 0 0 1 5 4 4 4 4 0 0 3 3 0
0 7 7 0 0 0 0 1 5 4 0 4 4 4 0 3 3 0
0 7 7 0 0 0 0 1 5 6 2 0 4 4 4 3 3 0
0 7 7 1 0 0 1 1 5 6 2 0 0 4 4 7 3 0
0 6 7 7 1 1 1 5 5 7 2 0 0 0 7 7 7 0
0 0 6 7 7 7 5 4 5 3 3 3 3 3 3 7 4 0
0 0 0 6 6 6 4 4 0 3 3 3 3 3 3 0 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Combined data
Figure 2.14.7 Assignment of the color palette registers for the color font RGB data RGB RGB RGB RGB RGB RGB RGB RGB 000b 0 001b 1 010b 2 011b 3 100b 4 101b 5 110b 6 111b 7 Color palette register ORCPT0 ORCPT1 ORCPT2 ORCPT3 ORCPT4 ORCPT5 ORCPT6 ORCPT7
88CS34-145
2003-03-25
TMP88CS34/CP34
The following shows how the color font shown on the preceding page is displayed by setting the color palette registers.
P 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 O 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 N 0 5 5 7 7 7 7 7 7 7 7 7 7 7 7 5 5 0 M 0 5 7 7 7 7 7 7 7 7 7 7 7 7 7 7 5 0 L 0 7 7 2 0 0 0 1 5 4 0 0 0 0 2 3 3 0 K 0 7 7 0 0 0 0 1 5 4 4 0 0 0 0 3 3 0 J 0 7 7 0 0 0 0 1 5 4 4 4 0 0 0 3 3 0 I 0 7 7 0 0 0 0 1 5 4 4 4 4 0 0 3 3 0 H 0 7 7 0 0 0 0 1 5 4 0 4 4 4 0 3 3 0 G 0 7 7 0 0 0 0 1 5 6 2 0 4 4 4 3 3 0 F 0 7 7 1 0 0 1 1 5 6 2 0 0 4 4 7 3 0 E 0 6 7 7 1 1 1 5 5 7 2 0 0 0 7 7 7 0 D 0 0 6 7 7 7 5 4 5 3 3 3 3 3 3 7 4 0 C 0 0 0 6 6 6 4 4 0 3 3 3 3 3 3 0 4 0 B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Color Palette Setting ORCPT0 00000000b ORCPT1 00000011b ORCPT2 00001100b ORCPT3 00110000b ORCPT4 00001111b ORCPT5 00111100b ORCPT6 00110011b ORCPT7 00111111b
Output Color Black Blue Green Red Cyan Yellow Magenta White
When background OFF, dots in which is written are displayed in black. When background ON, dots in which is written show no OSD display. However, if area-plane data and raste data exist in the background of the display these colors are displayed.
OSD output waveform when display line 9
R G B Y * Background * Background Y ON OFF
Figure 2.14.8
88CS34-146
2003-03-25
TMP88CS34/CP34
Note: Do not use the color font in the first character display position. The color font can be used in the second and subsequent character display positions. If you want to use a color font character in the first character display position as counted from the left side of the TV screen, display a transparent character in the first character display position, and use the color font in the second character display position. Prepare a monochrome font character with no dot as a transparent character. It is recommended that character code CRA 0x20H be prepared as a transparent character. Example of display First character display position: Transparent character. Second character display position: Color font
First character display position Transparent character
Second character display position Color font
88CS34-147
2003-03-25
TMP88CS34/CP34
(5) Dark color setting function The dark color setting function is intended to control OSD intermediate-value outputs, using High, High-Z, and Low outputs. Setting CPT1MD1 (bit 7 in ORCP1) to "1" enables this function. Producing 3-value outputs requires installing an external circuit.
R1 Microcontroller's RGB outputs R2 C2 To VCD IC C1 R3
Note:
The resistor and capacitor values used in the external circuit vary depending on the voltage potential you want to generate. Please make adjustments for yourself.
Figure 2.14.9 Example of an External Circuit for Creating Colors between Primary Colors
88CS34-148
2003-03-25
TMP88CS34/CP34
(6) Switching the OSD ROM area When the TMP88CS34 is initialized, it is configured for 383 characters of mono font and 96 characters of color font. By setting ROMACH (bit 5 of ORDON) to 1, this configuration can be changed to 447 characters of mono font and 64 characters of color font, as shown below.
In character colde order ROMACH CRA 000H 17FH 180H 0 ROMACH CRA 000H 17FH 180H 1
MCU Mode Address
EPROM Mode Address 05800H 0B7FFH 0B800H
MCU Mode Address
EPROM Mode Address 05800H 0B7FFH 0B800H 0C7FFH 0D000H 0DFFFH 0E800H 0E7FFH 0C800H 0CFFFH 0E400H 0E7FFH 0FC00H 0FFFFH
20000H Mono font data 384 characters 25FFFH 26000H Color font R data 277FFH 27800H
0CFFFH 0D000H
64 characters
20000H Mono font data 384 characters 25FFFH 26000H Color font R data 26FFFH 27800H Color font G data Color font B data 287FFH 29000H
96 characters
Color font G data 28FFFH 29000H Color font B data 0E7FFH 0E800H
1BFH 1C0H 1DFH 1E0H 1EFH 1F0H 2A7FFH 0FFFFH 1FFH
29FFFH Mono font data 27000H 32 characters 277FFH Mono font data 28C00H 16 characters 28FFFH Mono font data 2A400H 16 characters 2A7FFH
1DFH
In ROM address order ROMACH CRA 000H 17FH 180H 0 ROMACH CRA 000H 17FH 180H 1BFH 1C0H 277FFH 27800H 96 characters Color font G data 28FFFH 29000H Color font B data 1DFH 2A7FFH 0FFFFH 0E7FFH 0E800H 0CFFFH 0D000H 1DFH 180H 1BFH 1E0H 1EFH 180H 1BFH 1F0H 1FFH 1
MCU Mode Address
EPROM Mode Address 05800H 0B7FFH 0B800H
MCU Mode Address
EPROM Mode Address 05800H 0B7FFH 0B800H 0C7FFH 0C800H 0CFFFH 0D000H 0DFFFH 0E400H 0E7FFH 0E800H 0F7FFH 0FC00H 0FFFFH
20000H Mono font data 384 characters 25FFFH 26000H Color font R data
20000H Mono font data 384 characters 25FFFH 26000H Color font R data 64 characters/3 26FFFH Mono font data 27000H 32 characters 277FFH Color font G data 27800H 64 characters/3 287FFH Mono font data 28C00H 28FFFH Color font B data 29000H 64 characters/3 29FFFH Mono font data 2A400H 16 characters 2A7FFH 16 characters
Note:
Do not CRA code 000H at 88Cx34.
Figure 2.14.10
88CS34-149
2003-03-25
TMP88CS34/CP34 2.14.4 OSD Circuit Control
The OSD circuit performs control functions using the OSD control registers which reside in addreses 0001DH to 0001FH and 00024H to 00025H in the special function registers (SFR), and in addresses 00F80H to 00FCEH in the data buffer register (DBR). Section 2.14.6.8 shows the OSD control registers. The OSD control registers are used to set display start position, display character designs (that is, fringing, smoothing, color data, character size, and etc.), display memory addresses, and character codes. Setting the display on-off control bit, DON, (bit 0 in ORDON) to "1" enables display (starts display). Setting DON to "0" disables display (halts display).
2.14.5
OSD Control Register Write
There is a list of the OSD control registers on pages 199 to 201. When data is written into a shaded register, the data is transferred to the OSD circuit, and then the data becomes valid. After data is written into an unshaded register, the data is transferred to the OSD circuit, and then the data becomes valid. To transfer the contents of a control register to the OSD circuit, use data transfer request register RGWR (bit 2 in ORDON). Setting "1" in the RGWR register outputs the transfer request signal to the OSD circuit. Three instruction cycles later, transfer of the written data to the OSD circuit starts. While the data is being transferred, data transfer status monitoring flag RGWR (bit 2 in ORDON) is "1". When this transfer is completed, the flag is cleared to "0". Written data transfer register (1 bit) RGWR (Bit 2 in ORDON) "0" Initialized state Transfers written data to OSD circuit. "1" (After transfer, RGWR is reset to 0.) Note: Don't write "0" to RGWR.
88CS34-150
2003-03-25
TMP88CS34/CP34
(1) RGWR system
OSD circuit
Q D
LE
Transfer pulse by RGWR
1
Register specified by RGWR
Figure 2.14.11 RGWR System (2) Transfer timing 1. No display area When having set RGWR to "1" during no display area, the timing OSD register can be transferred is at the falling edge of HD signal.
HD
RGWR Register Set RGWR Register to "1" Data Transfer Pulse Transfer the contents of OSD registers into OSD circuit Clear RGWR
Figure 2.14.12 Data Transfer Timing in No Display Area 2. Display area (including any lines specified as display off by character size) When having set RGWR to "1" during display area, the timing OSD register can be transferred is at the falling edge of HD signal when the display line has been finished.
HD
Display Line RGWR Register Set RGWR Register to "1" Data Transfer Pulse Transfer the contents of OSD registers into OSD circuit Clear RGWR
Figure 2.14.13 Data Transfer Timing in Display Area
88CS34-151
2003-03-25
TMP88CS34/CP34 2.14.6 OSD Function
(1) P6 port output select function This function is used to select whether the contents of port P57, P67 to P64 will be output or I, R, G, B, Y/BL signals of the OSD circuit will be output on pins P57, P67 to P64. P57 port output select registers (1 bits): PIDS (bit 3 in ORP6S) PIDS
P57 I
2.14.6.1 Signal Control (Port I/O)
0
PIDS
Port
1
P67 to P64 port output select registers (4 bits): P67S, P66S, P65S, P64S, (bit 7 to 4 in ORP6S) P6nS
P64 P65 P66 P67 R G B Y/BL Port
0
P6nS
1
Note:
Be sure to write "0EH" to the ORP6S2 register (0x0FA1H).
(2) OSD pin output polarity control function This function is used to select the polarity of the OSD outputs for RGB, I and Y/BL. Output polarity control register (4 bits) ORIV) "0" "1" Active high Active low BLIV, YIV, RGBIV, IIV (bit 3 to 0 in
(3) OSD pin input polarity control Input polarity control Input polarity control register of RIN/GIN/BIN/Y/BLIN (2 bits) For Y/BLIN For RIN, GIN, and BIN Input polarity control YBLII (Bit 5 in ORIV) RGBII (Bit 4 in ORIV)
RGBII "0" Active high "1" Active low Input polarity control register of HD / VD (2 bits) For VD VDPOL (Bit 7 in ORIV) For HD HDPOL (Bit 6 in ORIV) Input polarity control VDPOL, HDPOL "0" Not invert input signal "1" Invert input signal Note: To direct P64 (R), P65 (G), and P66 (B) to produce three-value outputs (High, High-Z, and Low), be sure to write "0" to the output polarity control register (4 bits).
88CS34-152
2003-03-25
TMP88CS34/CP34
Input waveform to P70, P71 P71 ( VD ) P70 ( HD ) P71 ( VD ) P70 ( HD ) P71 ( VD ) P70 ( HD ) P71 ( VD ) P70 ( HD ) Register setting for the following waveform VDPOL HDPOL VDPOL HDPOL VDPOL HDPOL 0 0 1 0 0 1
VDPOL HDPOL
1 1
Figure 2.14.14 VD / HD input and VDPOL/HDPOL (4) Y/BL signal select function This function is used to select either Y or BL signal output from the Y/BL pin. Y/BL signal select register (1 bit) "0" "1" Y signal BL signal YBLCS (bit 7 in ORP6S)
Y signal output BL signal output Output in all OSD areas (Logical OR for R, G, B, Character data, Fringing data, area data, etc.) When EXBL is "0": Output in all display character areas When EXBL is "1": Output in the whole page
(5) I signal function select When PIDS (bit 3 in ORP6S) is set to "0", Port 57 (I pin) can be used as Half Transparency/Half Tone through an extra circuit. The I-pin output is made high only for the area planes. If you want to make the I-pin output high for area plane 1, set PISEL1 (bit 3 in the ORACL register) to "1". If you want to make the I-pin output high for area plane 2, set PISEL2 (bit 7 in the ORACL register) to "1". (6) R, G, B, Y/BL Internal/external signal select. Selects either R, G, B, and Y/BL signals from the internal OSD circuit, or RIN, GIN, BIN, and Y/BLIN signals from external input. R, G, B, Y/BL signal select registers (2 bits) "00" "01" "10" "11" MPXS1/MPXS0 (Bits 1 and 0 in ORP6S) Simultaneous output (Signal from the OSD circuit has higher priority.) Output of signal from internal OSD circuit Output of signal from external input Simultaneous output (External input signal has higher priority.)
88CS34-153
2003-03-25
TMP88CS34/CP34
2.14.6.2 OSD data output format control (1) Scan mode The double scan mode is used to handle non-interlaced scanning TV. When double scan mode is enabled, the vertical display counter increases every 2 scan lines and a vertical size of a dot is double. This function is enabled by setting VDSMD (bit 7 in ORETC) in the OSD control register to "1". Scan mode select register (1 bit) "0" "1" VDSMD (bit 7 in ORETC)
Normal mode Double scan mode
Note 1: The data written to those control register is transferred to the OSD circuit and become valid when the data is written. Note 2: When OSD circuit is used on an interlace scanning TV, a jitter elimination circuit must be enabled and set AFLD to "1" in JECR. Table 2.14.3 The Difference of 2 types of Scan Mode Normal mode
Specification Unit of vertical display start position 1 dot height One scanning line
Double scan mode
Two scanning lines Normal mode height 2
Normal mode
Double scan mode
Normal mode
Double scan mode
Interlace scanning
Non-interlace scanning
Figure 2.14.15 Scan Mode
88CS34-154
2003-03-25
TMP88CS34/CP34
2.14.6.3 Display Position Control (1) Code display position setting 1. Horizontal display start position The horizontal display start position can be set in 256 steps by writing to OSD control registers HS17 to HS10 (bit 7 to 0 in ORHS1). The value is in common with all lines. Specification unit: 2 TOSC Specification steps: 256 Specification horizontal display start position: Line 1 to 12: HS17 to HS10 (ORHS1) HS1 (HS17 to HS10) H 2TOSC 22TOSC (Line1 to 12)
Note 1: TOSC; One cycle of OSD oscillation. Note 2: The data written to these control registers is transmitted to OSD circuit by setting RGWR (bit 2 in ORDON) to "1". 2. Vertical display start position The vertical display start position can be specified for each display line using 625 steps by writing to VSn9 to VSn0 (in ORVSn (n; 1 to 12)). Specification unit: 1 scan line Specification steps: 512 Specification vertical display start position: Line1: VS19 to VS10 (ORVS 1) Line2: VS29 to VS20 (ORVS 2) . . . Line12: VS129 to VS120 (ORVS 12) Line n: VSn Note 1: THD; One cycle of HD signal. Note 2: The data written to these control registers is transmitted to OSD circuit by setting RGWR (bit 2 in ORDON) to "1". Note 3: If display lines are overlapped each other, previous display line is enabled and next line is disabled. If vertical display start positions of two or more lines are set on same value, high priority line is enabled. Lines of OSD (VS1 to VS12) are fixed priority levels as follows: VS1 VS2 VS3 VS12 Set the vertical display start position not to overlap display lines.
VS5 (display on, small character) VS2 (display canceled, middle character)
(VSn9 to VSn0) H
1THD (n; 1 to 12)
VS3 (display on, small character)
Occasion of overlapping Note 4: The line which is displayed off is managed as a small size character line. Note 5: Transfer the contents of vertical display start position registers into OSD circuit before the position of the scanning line coincides with their own vertical display start position.
88CS34-155
2003-03-25
TMP88CS34/CP34
(2) Area display position setting The planes have the priority such as Code plane Raster plane. 1. Horizontal display start position The horizontal display start position can be set in 512 steps by writing to OSD control registers AHSn8 to AHSn0 (bit 8 to 0 in ORAHSn). And also display stop position is correspond to AHEn8 to AHEn0 (bit 8 to 0 in ORAHEn). (n; 1 to 2) Horizontal display start position AHSn AHEn (AHSn8 to AHSn0)H (AHEn8 to AHEn0)H 2TOSC 2TOSC Area plane 1 Area plane 2
Note 1: TOSC: One cycle of OSD oscillation. Note 2: If the horizontal display start position for characters is the same as that for areas, the two positions are not displayed at the same time. The horizontal display start position for characters is displayed 16 TOSC (corresponding to a register value of 8) later than that for areas. 2. Vertical display start position The vertical display start position can be set in 625 steps by writing to OSD control registers AVSn9to AVSn0 (bit 9 to 0 ORAVSn). And also display stop position is correspond to AVEn9 to AVEn0 (bit 9 to 0 in ORAVEn). (n; 1 to 2) Vertical display start position AVSn AVEn Note: (AVSn9 to AVSn0)H (AVEn9 to AVEn0)H THD THD
THD: One cycle of HD signal.
HD
VS1 VS2
AVS1 AVE1
AVS2 AVE2
HS1
12
34 5 6 7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Area plane 1 AHE1
Code plane 1 Code plane 2
12345678 AHS1
VD
Area plane 2
HS1 AHS2
SS 1 2 3 4 5 6 7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SS Code plane 9
SS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SS Code plane 10 SS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SS Code plane 11 SS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SS Code plane 12
AHE2
Figure 2.14.16 TV Scan Image
88CS34-156
2003-03-25
TMP88CS34/CP34
2.14.6.4 Character Ornamentation Control (1) Character sizes Character size can be selected line by line from 4 sizes. And display on/off also can be set line by line. Small, middle, large and double height character size and display on/off can be set with OSD control registers CSn (n 1 to 12, ORCS4, ORCS8, ORCS12) in the OSD control registers. Character sizes: 4 sizes (Small, middle, large and double height) Character size and display on/off specification unit: Line Character size select/display on/off register (2 bits Line 1: CS1 Line 2: CS2 : : Line 12: CS12 Table 2.14.4 Character Size and Display On/Off Specifications (n
CSn (high-order bit) 1 1 0 1 0 CSn (low-order bit) 1 0 1 0 0 Character size Small-size character Medium-size character Large-size character Double-height character
12)
1 to 12 and m
1 to 12)
DCSCn (double-height specification) 0 0 0 1 0
Display on/off On On On On Off
Note 1: To display a double-height character, write "10" and "1", respectively, to CSn (medium-size character specification) and DCSCm (double-height display specification). If DCSCm and CSn are, respectively, "0" and "10", medium-size characters are displayed. Note 2: If the character size specification (CSn) is "11" or "01", no double-height character can be displayed. Note 3: Do not specify to modify double-height characters (such as fringing, smoothing, and slanting) because such specifications hamper normal display. Note 4: The display off line operates like the width of small character size line thought the character is not displayed. Note 5: The data written to these control registers is transmitted to OSD circuit by setting RGWR (bit 2 in ORDON) to "1". Note 6: When OSD circuit is used on an interlace scanning TV, a jitter elimination circuit must be enabled and set AFLD to "1" in JECR. Note 7: When VDSMD and AFLD are "0", only character of even display dot is displayed. (refer to 2.16 a jitter elimination circuit)
88CS34-157
2003-03-25
TMP88CS34/CP34
Table 2.14.5 Dot Size and Character Size VDSMD 0 (normal mode) Dot size
EULAn 0 (underline off) Small-size character Medium-size character Large-size character Double-height character EULAn 1 (underline on) Small-size character Medium-size character Large-size character Double-height character 1TOSC 0.5THD 2TOSC 1THD 4TOSC 2THD 1TOSC 1THD 1TOSC 0.5THD 2TOSC 1THD 4TOSC 2THD 1TOSC 1THD
VDSMD 1 (double-scan mode) Dot size
1TOSC 1THD 2TOSC 2THD 4TOSC 4THD 1TOSC 2THD 1TOSC 1THD 2TOSC 2THD 4TOSC 4THD 1TOSC 2THD
Character size
16TOSC 9THD 32TOSC 18THD 64TOSC 36THD 16TOSC 18THD 16TOSC 12THD 32TOSC 24THD 64TOSC 48THD 16TOSC 24THD
Character size
16TOSC 18THD 32TOSC 36THD 64TOSC 72THD 16TOSC 36THD 16TOSC 24THD 32TOSC 48THD 64TOSC 72THD 16TOSC 48THD
Note:
TOSC
one OSD oscillation cycle. THD
one HD signal cycle.
88CS34-158
2003-03-25
TMP88CS34/CP34
Small
Middle
Double height
Large
Figure 2.14.17 Character Size (2) Smoothing function The smoothing function is used to make characters look smooth. Enabling smoothing displays 1/4 dot between two dots connecting corner to corner within a character. Small size character and color font can not be enabled smoothing. Smoothing is enabled by setting ESMZ (bit 4 in ORETC) in the OSD control register to "1". Smoothing specification unit: Display page Smoothing specification register (1 bit) "0" "1" Disable smoothing Enable smoothing ESMZ (bit 4 in ORETC)
Note 1: Data of the register is transferred to the OSD circuit and become valid when the data is written. Note 2: The smoothing function is invalid for the color font.
Before
After
Before
After
Available form for Smoothing
Invalid form for Smoothing
Figure 2.14.18 Available Form and Invalid Form for Smoothing
88CS34-159
2003-03-25
TMP88CS34/CP34
Original character
Smoothing
Figure 2.14.19 Smoothing Example (3) Fringing function The fringing function is used to display a character with a fringe width is 1 dot in a different color from that of the character. When a character is displayed with the maximum of 18 vertical dots and 16 horizontal dots, the fringe exceeds right and left of the character display area. No vertical fringing is displayed out of the character display area. If there is an adjacent character that outer dot is active, then this dot will overrule the fringe in the horizontal direction. Underlines are not fringed. Fringing is enabled for each line by setting EFR1 to EFR8 (OREFR8) and EFR9 to EFR12 (OREFR12) in the OSD control register to "1". A color for fringe is specified common to all lines using OSD control registers, RFDT, GFDT, and BFDT (bit 2 to 0 in ORBK). Fringing specification unit: Line Fringing enable register (1 bit "0" "1" Fringe colors: 8 or 27 Fringe color specification unit: Display page Fringe color register (3 bits) RFDT, GFDT, BFDT (bit 2 to 0 in ORBK) 12) EFRn (n; 1 to 8) (OREFR8), EFRn (n; 9 to 12) (OREFR12)
Disable fringing Enable fringing
Note 1: The fringe of 1st column character does not exceed left, and the fringe of 32th character does not exceed right. Note 2: Do not specify fringing for the color font. Note 3: Do not specify fringing for characters for which double-height display is specified.
88CS34-160
2003-03-25
TMP88CS34/CP34
Table 2.14.6 Fringe Color RFDT
0 0 0 0 1 1 1 1
GFDT
0 0 1 1 0 0 1 1
BFDT
0 1 0 1 0 1 0 1
Figure color
Setting color of ORCPT0 Setting color of ORCPT1 Setting color of ORCPT2 Setting color of ORCPT3 Setting color of ORCPT4 Setting color of ORCPT5 Setting color of ORCPT6 Setting color of ORCPT7
Vertical indicate area 18 dots
Before Fringing Disable underline
After Fringing
Vertical indicate area 24 dots
Before Fringing Enable underline a) Small character, Normal mode
After Fringing
Figure 2.14.20 (a) Fringing Example
88CS34-161
2003-03-25
TMP88CS34/CP34
Vertical indicate area 18 dots
Before Fringing Disable underline
After Fringing
Vertical indicate area 24 dots
Before Fringing Enable underline
After Fringing
b) Small character, Double scan mode
Figure 2.14.21 (
) Fringing Example
88CS34-162
2003-03-25
TMP88CS34/CP34
Vertical indicate area 18 dots
Before Fringing Disable underline
After Fringing
Vertical indicate area 24 dots
Before Fringing Enable underline
After Fringing
c) Middle/Large character, Normal mode
Figure 2.14.22 (
) Fringing Example
88CS34-163
2003-03-25
TMP88CS34/CP34
Vertical indicate area 18 dots
Before Fringing Disable underline
After Fringing
Vertical indicate area 24 dots
Before Fringing Enable underline
After Fringing
d) Middle/Large character, Double scan mode
Figure 2.14.23 (
) Fringing Example
88CS34-164
2003-03-25
TMP88CS34/CP34
(4) Double-height display function It is possible to display a character having the same horizontal size as for the small-size character and the same vertical size as for the medium-size character. This function can be realized by specifying medium-size character display for the character size and setting up the double-height display setting register (ORDCSC). Its specification unit is the row. Double-height display enable unit: Row Double-height display enable register (1 bit Character size specification: "10" is set in CSn (n ORCS12). 12): DCSCn (n 1 to 12) (ORDCSC register) 1 to 12; ORCS4, ORCS8, and
Small-size character
Medium-size character
Double-height character
Figure 2.14.24 Double-Height Character Display Note: Do not specify the fringing, smoothing, or slanting character modification function for a row where double-height display is specified.
88CS34-165
2003-03-25
TMP88CS34/CP34
(5) Displaying a Small-Size Character Consisting of 26 Vertical and 18 Horizontal Dots It is possible to display small-size characters at vertical intervals of 26 scanning lines. This function is realized by specifying small-size character display and setting up the 26-dot vertical display setting register ORCCD. This specification can be made in line units. 26-dot vertical display enable unit: Row 26-dot vertical display enable register (1 bit 12): CCDn (n register) 1 to 12) (ORCCD
Character size specification: "11" is set in CSn (n ORCS12).
1 to 12; ORCS4, ORCS8, and
Small-size character 26-dot vertical display
Figure 2.14.25 26-dot Vertical Display (6) Background function The background color is the color of all backgrounds including the background of the character area (see Table 2.14.5). The background function is specified in screen units by setting the EBKGD OSD control register (bit 7 in the ORRCL register) to "1". Using the ECBKD OSD control register (bit 3 in the ORDSN register) can enable/disable the character-specific background color. The background color is specified, using the RBDT, GBDT, and BBDT OSD control registers (bits 6 to 4 in the ORBK register). Setting the ECHDSN OSD control register (bit 3 in the ORDON register) to "1" specifies SLNT (bit 6 in the ORDSN register) and EUL (bit 5 in the ORDSN register), respectively, as RBDT and GBDT. A background color different from that of the screen can be set up as a character-specific background. Background color enable units: Screen and character Background enable register (2 bits) Screen unit: EBKGD (bit 7 in the ORRCL register) Character unit: ECBKD (bit 3 in the ORDSN register) Background color specification units: Screen and character Background color specification register If ECHDSN 0: RBDT, GBDT, and BBDT (bits 6 to 4 in the ORBK register) If ECHDSN 1: RBDT, GBDT (bits 6 to 4 in the ORBK register), SLNT (corresponding to RBDT), and EUL (corresponding to GBDT)
88CS34-166
2003-03-25
TMP88CS34/CP34
Table 2.14.7 Background Color Control OSD control register EBKGD
0 0 1 1
ECBKD
0 1 0 1
Display status
No background is displayed. No background is displayed. No background is displayed. A background is displayed.
Table 2.14.8 Character-Specific Background Color Setting Function Register name
SLNT Character modification specification register EUL BLF ECBKE
Function
Slanting Underlining Blanking Character-specific background enable
Character-specific background color setting (ECHDSN) 0 1
RBDT (background color of red) GBDT (background color of green)
Note1: When the ECHDSN is set to "1", the background color is specified by RBDT (red) and GBDT (green) bits.In this case, ORCPT0,ORCPT2,ORCPT4 and ORCPT6 are available for color pallet. Note 2: OSD output isn't done, and a video signal is indicated in the background area in case of EBKGD=0, ECBKD=0 and EBKGD=1, ECBKD=0.A background area becomes transparent in case of EBKGD=0 and ECBKD=1. That color is indicated when it is piled up and indicated with the area plane. The background color specified in case of EBKGD=1 and ECBKD=1 is indicated. Table 2.14.9 Background Color RBDT
0 0 0 0 1 1 1 1
GBDT
0 0 1 1 0 0 1 1
BBDT
0 1 0 1 0 1 0 1
Background color
Setting color of ORCPT0 Setting color of ORCPT1 Setting color of ORCPT2 Setting color of ORCPT3 Setting color of ORCPT4 Setting color of ORCPT5 Setting color of ORCPT6 Setting color of ORCPT7
88CS34-167
2003-03-25
TMP88CS34/CP34
Character color : Cyan Background color : Yellow
Scanning line
Scanning line
R G B Y BL 1) Disable Background
R G B Y BL 2) Enable Background
Figure 2.14.26 Background Function Note: When the background function is enabled, the line enable the fringing function should not start with a blank character. If it starts with a blank character, a fringe is displayed to the left of the blank character.
88CS34-168
2003-03-25
TMP88CS34/CP34
2.14
2.14.6.5 OSD FDisplay Screen Control (1) Display on/off This function is used to display characters specified for on/off display. Display on/off specification unit: Display page Display on/off specification register (1 bit) *** DON (bit 0 in ORDON) "0" *** Disable display "1" *** Enable display Note: Do not start STOP mode during display is enable.
(2) Window function This function is used to set upper and lower limit of display page. Window upper limit is specified by WVSH (ORWVSH). Window lower limit is specified by WVSL (ORWVSL). This function is enabled by setting EWDW (bit 1 in ORDON ) in the OSD control register to 1. Window specification unit: Display page Window function enable specification register (1 bit) *** EWDW (bit 1 in ORDON) "0" *** Disable window function "1" *** Enable window function Window upper limit specification register (10 bits) *** WVSH9 to 0 (ORWVSH) Window lower limit specification register (10 bits) *** WVSL9 to 0 (ORWVSL) Window upper and lower limit position *** When VDSMD is "0" (Normal mode): WVSH WVSL WVSH WVSL (WVSH9 to WVSH0) H (WVSL9 to WVSL0) H (WVSH9 to WVSH0) H (WVSL9 to WVSL0) H THD THD 2THD 2THD
When VDSMD is "1" ( Double scan mode):
Note 1: THD; One cycle of HD signal Note 2: WVSL WVSH "1"
Note 3: Modify the value of window upper and lower limit register and the value of EWDW during VD signal is low. Note 4: It is recommendable that the window function is always enabled (EWDW and set WVSH to "01H", WVSL to "1FEH". "1")
Note 5: Characters and symbols at scanning line specified by WVSL are not displayed.
88CS34-169
2003-03-25
TMP88CS34/CP34
HD
Background color
WVSH
Area plane color
Raster color
Picture
VD
SS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SS AHS1 SS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SS SS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SS
WVSL
Picture
Note:
Window display: ON, Area plane display: ON, Background color display: ON, Raster plane display: ON
Figure 2.14.27 Display Example
Display off
WVSH Display
Figure 2.14.28 If WVSH is on a Code Plane
88CS34-170
2003-03-25
TMP88CS34/CP34
(3) Full-raster blanking function Full-raster blanking function is used to color the entire background for the display area (TV screen). When using the full-raster blanking function, set YBLCS (bit 2 in ORP6S) to "1", output BL signal from Y/BL pin, because Y signal cannot delete whole display page from video signal. This function is specified for each display page by setting EXBL (bit 6 in ORRCL) in the OSD register to "1". Full-raster blanking specification unit: Display page Full-raster blanking enable register (1 bit) *** EXBL (bit 6 in ORRCL) "0" *** Disable full-raster blanking "1" *** Enable full-raster blanking Full-raster blanking color specification *** registers (3 bits) Table 2.14.10 Raster Plane Color RCLR
0 0 0 0 1 1 1 1
RCLR, RCLG, RCLB (bit 2 to 0 in ORRCL)
RCLG
0 0 1 1 0 0 1 1
RCLB
0 1 0 1 0 1 0 1
Raster plane color
Setting color or ORCPT0 Setting color or ORCPT1 Setting color or ORCPT2 Setting color or ORCPT3 Setting color or ORCPT4 Setting color or ORCPT5 Setting color or ORCPT6 Setting color or ORCPT7
88CS34-171
2003-03-25
TMP88CS34/CP34
(4) Area plane function Area plane function is used to display square area to two points on a screen. Two planes operate independently. They are displayed according to the priority (area plane 1 area plane 2). See area plane display position setting in section 2.14.6.3 (2) how to set display positions for each area. Each area plane is set to ON or OFF by AON2 and AON1 (bit 5 and bit 4 in ORRCL). Area plane colors are set by ACLRx, ACLGx, ACLBx (bit 6 to bit 4 and bit 2 to bit 0 in ORACL, x 1, 2). Area plane colors: 8 or 27 Area plane specification unit: plane Area plane color specification register (6 bit) Area plane 1: ACLR1/ACLG1/ACLB1 (bit 2 to 0 in ORACL) Area plane 2: ACLR2/ACLG2/ACLB2 (bit 6 to 4 in ORACL) Table 2.14.11 Area Plane Color ACLRx
0 0 0 0 1 1 1 1
ACLGx
0 0 1 1 0 0 1 1
ACLBx
0 1 0 1 0 1 0 1
Area plane color
Setting color of ORCPT0 Setting color of ORCPT1 Setting color of ORCPT2 Setting color of ORCPT3 Setting color of ORCPT4 Setting color of ORCPT5 Setting color of ORCPT6 Setting color of ORCPT7 (x: 1, 2)
(5) I-pin function The I-pin output becomes valid only for area planes. Resetting the PIDS OSD control register (bit 3 in the ORP6S register) to "0" causes P57 to work for I-pin output. If you want to produce an I-pin output for area plane 1, set the PISEL1 OSD control register (bit 3 in the ORACL register) to "1". If you want to produce an I-pin output for area plane 2, set the PISEL2 OSD control register (bit 7 in the ORACL register) to "1". The I-pin output depends on the display priority of the area planes.
88CS34-172
2003-03-25
Example 1 0, 1> 0, 1>
Example 2 Example 3 Area 2 Halftone Area 1 A B C D
dot
PISEL1 PISEL2 Area 2 Area 1 Halftone A B C D Area 2 Halftone
0 1
PISEL1 PISEL2
1 0
PISEL1 PISEL2
1 1
A
dot
Area 1 Halftone
dot
B C D Character display area Area where any of font colors R, G, and B is high
(6) Examples of OSD outputs
A Y BL
I
A
I
A
I Y BL
Y
Figure 2.14.29 OSD Output Examples (a)
88CS34-173
B Y BL I C I Y BL D I Y BL
BL
B
I
B
I Y BL
Y
BL
C
I
C
I Y BL
Y
BL
D
I
D
I Y BL
Y
TMP88CS34/CP34
2003-03-25
BL
Example 4 dot
0, 1)> 0, 1)> Raster Area 2 PISEL1 PISEL2 0 1 A B C D
dot
Example 5 Example 6 0, YBLCS
0, 1)>
Raster Area 2 Halftone PISEL1 PISEL2 Area 1 Halftone 1 0 A B C D
dot
PISEL1 PISEL2
1 1
Area 1
Character display area Area where any of font colors R, G, and B is high
A, D I A, B, C, D Y BL I Y
A, D I Y BL
Figure 2.14.30 OSD Output Examples (b)
88CS34-174
Y
BL
B, C I
B, C I Y BL
BL
TMP88CS34/CP34
2003-03-25
Example 7 In patterns 1, 2 and 3, area plane 1, rather than area plane 2, is displayed. 1> In examples 7, 8 and 9, area plane 1, rather than area plane 2, is displayed.
Example 8 Example 9 1>
In patterns 1, 2 and 3, area plane 1, rather than area plane 2, is displayed.
Area 2 Halftone A B C D
dot dot
PISEL1 PISEL2 Area 2 A B C D Character display area Area where any of font colors R, G, and B is high Area 1 Halftone A B C D
0 1
PISEL1 PISEL2
1 0
Area 2 Halftone Area 1 Halftone
dot
PISEL1 PISEL2
1 1
Area 1
Figure 2.14.31 OSD Output Examples (c)
88CS34-175
A, B, I C, D, E BL
A, B, I C, D, E BL
A, B, I C, D, E BL
TMP88CS34/CP34
2003-03-25
Example 10 1)> Example 11 dot
Example 12 1, YBLCS
1)>
0 1 Area 1 Halftone
Raster Area 2
Raster Area 2 Halftone Area 1 Halftone
dot
PISEL1 PISEL2
1 1
A
dot
Area 1
B C D Character display area Area where any of font colors R, G, and B is high
Figure 2.14.32 OSD Output Examples (d)
88CS34-176
A, B, I C, D, E BL
A, B, I C, D, E BL
A, B, I C, D, E BL
TMP88CS34/CP34
2003-03-25
TMP88CS34/CP34
2.14.6.6 Interrupt Control (1) Display line counter The display line counter indicates number of display line (s) by OSD circuit on the TV screen. The display line counter is a 4-bit counter which is initialized to "0" by the falling edge of the VD signal and which increments when last scanning of each display line is completed (falling edge of the HD signal). It is necessary to be read out display line counter several times, because it does not synchronize CPU clock. Display line counter register (4 bits) *** DCTR (bit 3 to 0 in ORIRC) "0000" *** No display line is completed. "0001" *** 1st display line is completed. "0010" *** 2nd display line is completed. to to "1111" *** 15th display line is completed.
Display line counter m 0
VD signal
1st Display Line 2nd Display Line 1
Display on Display off
2
3rd Display Line 3 4th Display Line with all blank characters : : 10th Display Line
Display on Display on
9
4
Display on
10
11th Display Line 11
Display on
12th Display Line
Display on
Note 1:
The display line counter also increments when a line with all blank characters or a line with display off is specified.
Note 2:
When display lines are overlapped each other, previous display line is enabled and next line is disabled. At this time, the display line counter does not increment for disabled line.
12
Figure 2.14.33 Display Line Counter
88CS34-177
2003-03-25
TMP88CS34/CP34
(2) Interrupt generator circuit An interrupt request is generated when a falling edge of VD signal or when line counter (DCTR) is counted to the certain value specified by ISDC. Interrupt source select register (1 bit): SVD (bit 4 in ORIRC) "0" "1" *** *** Interrupt request generated when the display line counter (DCTR) is counted to the certain value which is specified by ISDC. Interrupt request is generated when a falling edge of VD signal.
Interrupt generation line specification register (4 bits) *** ISDC (bit 3 to 0 in ORIRC) "0000" "0001" "0010" to "1111" *** *** *** *** Interrupt request generated when the display line counter is cleared. Interrupt request generated at end points of the last scanning line of the first display line Interrupt request generated at end points of the last scanning line of the 2'nd display line Interrupt request generated at end points of the last scanning line of the 15'th display line
2.14.6.7 Display Memory Access (1) Display memory The display memory is accessed for two purposes, one for writing data to the display memory, and one for reading data from the display memory. Display memory address specification registers *** DMA8 to MDA0 (ORDMA) (9 bits) Display memory data write registers Character code write register (9 bits) Character ornamentation data write registers (6 bits) Character-specific background on/off specification register (1 bit) "0" "1" *** *** *** CRA8 to CRA0 (ORCRA) *** SLNT, EUL, BLF, RDT, GDT, and BDT (ORDSN) *** ECBKD (ORDSN register)
Display memory bank select register MBK (bit 1 in ORETC) When writing either character code or character ornamentation data When writing both character code and character ornamentation data
Note 1: These control registers have a characteristic that immediately when a value is written to the register, the content of the register is transferred as valid data to the OSD circuit/display memory. Note 2: The data written to the display memory takes effect at the same time it is written. When character code or character ornamentation data is written to the display memory while it is displaying some character, the character may not be displayed correctly. When writing data to the display memory, make sure no character is being displayed in the memory location where you are going to write data. Note 3: When writing data to or reading data from the display memory, do not use two-byte transfer instructions such as "LDW(HL),mn LD rr, (pp)." Otherwise, erroneous data may be written to the display memory or data may be written to an incorrect address. Note 4: Allow for at least two instruction cycles between a display memory address write instruction and a data write or read instruction. Also, when continuous writing data to or reading data from the display memory, allow for at least two instruction cycles between one write or read instruction and the next. Otherwise, erroneous data may be written to the display memory or data may be written to an incorrect address. Note 5: When setting display memory addresses, always be sure to write all of 9 address bits sequentially in order of DMA8 and DMA7 to DMA0.
88CS34-178
2003-03-25
TMP88CS34/CP34
1. Normal mode In normal mode, the display memory addresses are automatically incremented each time data is read from or written to the memory. Because addresses are automatically incremented, this mode may be used for reading from or writing data to multiple continuous addresses simultaneously. (a) When writing either character code or character ornamentation data (1) Set MFYWR, MBK, and RDWRV all to 0. (2) Write the most significant address bit of the display memory to DMA8. Go on and write the 8 low-order address bits of the display memory to DMA7 to DMA0. (3) Writing character code or character ornamentation data Writing character code Write the most significant bit of character code to CRA8. Go on and write the 8 low-order bits of character code to CRA7 through CRA0. At this point in time, the 9 bits of character code written are transferred to the display memory, and DMA8 to DMA0 are automatically incremented. Writing character ornamentation data Write character ornamentation data to SLNT, EUL, BLF, ECBKD, RDT, GDT, and BDT. At this point in time, the character ornamentation data written are transferred to the display memory, and DMA8 to DMA0 are automatically incremented. (4) To write data (character code or character ornamentation data) to continuous addresses, repeat step (3). (b) When writing character code and character ornamentation data at a time (1) Set MFYWR to 0, MBK to 1, and RDWRV to 0. (2) Write the most significant address bit of the display memory to DMA8. Go on and write the 8 low-order address bits of the display memory to DMA7 to DMA0. (3) Write character ornamentation data to SLNT, EUL, BLF, ECBKD, RDT, GDT, and BDT. At this point in time, the character ornamentation written are transferred to the display memory. (4) Write the most significant bit of character code to CRA8. Go on and write the 8 low-order bits of character code to CRA7 to CRA0. At this point in time, the 9 bits of character code written and the character ornamentation data written in step (3) are transferred to the display memory, and DMA8 to DMA0 are automatically incremented. (5) To write data to continuous addresses, repeat steps (3) and (4).
88CS34-179
2003-03-25
TMP88CS34/CP34
(a) When reading either character code or character ornamentation data (1) Set MFYWR to 0, MBK to 0, and RDWRV to 1. (2) Write the most significant address bit of the display memory to DMA8. Go on and write the 8 low-order address bits of the display memory to DMA7 to DMA0. (3) Reading character code or character ornamentation data Reading character code Read the most significant bit of character code to CRA8. Go on and read the 8 low-order bits of character code to CRA7 to CRA0. At this point in time, DMA8 to DMA0 are automatically incremented. Reading character ornamentation data Read character ornamentation data SLNT, EUL, BLF, ECBKD, RDT, GDT, and BDT. At this point in time, DMA8 through DMA0 are automatically incremented. (4) To read data (character code or character ornamentation data) from continuous addresses, repeat step (3). (b) When reading character code and character ornamentation data at a time (1) Set MFYWR to 0, MBK to 1, and RDWRV to 1. (2) Write the most significant address bit of the display memory to DMA8. Go on and write the 8 low-order address bits of the display memory to DMA7 to DMA0. (3) Read character ornamentation data SLNT, EUL, BLF, ECBKD, RDT, GDT, and BDT. (4) Read the most significant bit of character code to CRA8. Read the 8 low-order bits of character code to CRA7 to CRA0. At this point in time, DMA8 to DMA0 are automatically incremented. (5) To read data from continuous addresses, repeat steps (3) and (4). 2. Read-modify-write mode When writing data in read-modify-write mode, the display memory addresses are automatically incremented as in normal mode, but when reading data in this mode, the memory addresses are not automatically incremented. Therefore, immediately after executing a read from some display memory address, you can execute a write to the same display memory address. After executing a write, the display memory addresses are automatically incremented. (a) Reading/writing either read-modify-write mode character code or character ornamentation data in
(1) Set MFYWR to 1 and MBK to 0, and RDWRV to 1. (2) Write the most significant address bit of the display memory to DMA8. Go on and write the 8 low-order address bits of the display memory to DMA7 to DMA0. (3) Reading character code or character ornamentation data Reading character code Read the most significant bit of character code to CRA8. Read the 8 low-order bits of character code to CRA7 to CRA0. DMA8 to DMA0 are not incremented. Reading character ornamentation data Read character ornamentation data SLNT, EUL, BLF, ECBKD, RDT, GDT, and BDT. DMA8 to DMA0 are not incremented.
88CS34-180
2003-03-25
TMP88CS34/CP34
(4) Writing character code or character ornamentation data Set RDWRD to "0". Writing character code Write the most significant bit of character code to CRA8. Go on and write the 8 low-order bits of character code to CRA7 to CRA0. At this point in time, the 9 bits of character code written are transferred to the display memory, and DMA8 to DMA0 are automatically incremented. Writing character ornamentation data Write character ornamentation data to SLNT, EUL, BLF, ECBKD, RDT, GDT, and BDT. At this point in time, the character ornamentation data written are transferred to the display memory, and DMA8 to DMA0 are automatically incremented. (5) To continue executing read-modify-write operations, repeat steps (1) to (4). To read/write data (character code or character ornamentation data). To continue executing read modify-write mode from continuous addresses, repeat steps (3) and (4). (b) Reading/writing both character read-modify-write mode (1) Set MFYWR to 1, MBK to 1. (2) Write the most significant address bit of the display memory to DMA8. Go on and write the 8 low-order address bits of the display memory to DMA7 to DMA0. (3) Read character ornamentation data SLNT, EUL, BLF, ECBKD, RDT, GDT, and BDT. At this point in time, DMA8 to DMA0 are not incremented. (4) Read the most significant bit of character code to CRA8. Read the 8 low-order bits of character code to CRA7 to CRA0. At this point in time, DMA8 to DMA0 are not incremented. (5) Set RDWRD to "0". (6) Write character ornamentation data to SLNT, EUL, BLF, ECBKD, RDT, GDT, and BDT. At this point in time, the character ornamentation data written is transferred to the display memory. (7) Write the most significant bit of character code to CRA8. Go on and write the 8 low-order bits of character code to CRA7 to CRA0. At this point in time, the 9 bits of character code written and the character ornamentation data written in step (6) are transferred to the display memory, and DMA8 to DMA0 are automatically incremented. (8) To continue executing read-modify-write operations, repeat steps (1) to (7). (To read/write data to and from continuous addresses in read-modify-write mode, repeat steps (3) to (7).) code and character ornamentation data in
88CS34-181
2003-03-25
TMP88CS34/CP34
Table 2.14.12 Address Increment RD WR Character Character ornamentation Character code ornamentation Character code
MFYWR MFYWR 0 1 MBK MBK MBK MBK 0 1 0 1 INC INC INC INC INC INC INC INC INC
INC: Automatic address increment at read or write. : No address change at data read or write.
Example: Setting a character code (020H) to the display memory (Address: 120H) and setting a character ornamentation (001H) for character code 020H and display memory address 120H. 1. MBK 0 ; Set display memory LD (0x25), 0x01 LD (0x24), 0x20 ; Set character code LD (0x1F), 0x00 LD (0x1E), 0x20 ; Set display memory again LD (0x25), 0x01 LD (0x24), 0x20 ; Set character ornamentation LD (0x1D), 0X01 2. MBK 1 ; Set display memory LD (0x25), 0x01 LD (0x24), 0x20 ; Set character ornamentation LD (0x1D), 0X01 ; Set character code LD (0x1F), 0x00 LD (0x1E), 0x20
Note 1: To write character data into the display memory, first write into register CRA8 and then write into registers CRA7 to CRA0. When data is written into registers CRA7 to CRA0, DMA is incremented. It is impossible to write into the display memory for CRA7 to CRA0 alone. If no data is written into register CRA8 while data is written into registers CRA7 to CRA0, the value previously written into register CRA8 is written into the associated display memory. Note 2: To read data from the display memory, first read from register CRA8, and then read from registers CRA7 to CRA0. When data is read from registers CRA7 to CRA0, DMA is incremented. Note 3: There should be a time interval of at least two machine cycles between a DMA set instruction and a data write/read instruction. There should be a time interval of at least two machine cycles between a data write instruction and a data read instruction.
88CS34-182
2003-03-25
TMP88CS34/CP34
(2) Characters If ROMACH (bit 5 in ORDON) 0 Characters: 383 monochrome font characters and 96 color font characters Character specification register (9 bits): CRA8 to CRA0 (bits 8 to 0 in the ORCRA register) Character codes: User-programmable in character ROM Monochrome font codes "001H" to "17FH" Color font codes "180H" to "1DFH" If ROMACH (bit 5 in ORDON) 1 Characters: 447 monochrome font characters and 64 color font characters Character specification register (9 bits): CRA8 to CRA0 (bits 8 to 0 in the ORCRA register) Character codes: User-programmable in character ROM Monochrome font codes "001H" to "17FH", "1C0H" to "1DFH", "1F0H" to "1FFH" Color font codes "180H" to "1BFH" (3) Character color Character colors: 8 or 27 Character color specification unit: Character Character color specification register (3 bits): RDT/GDT/BDT (bit2 to 0 in ORDSN) Table 2.14.13 Character Color RDT
0 0 0 0 1 1 1 1
GDT
0 0 1 1 0 0 1 1
BDT
0 1 0 1 0 1 0 1
Character color
Setting color of ORCPT0 Setting color of ORCPT1 Setting color of ORCPT2 Setting color of ORCPT3 Setting color of ORCPT4 Setting color of ORCPT5 Setting color of ORCPT6 Setting color of ORCPT7
(4) Blinking function Blinking function is used to blink display characters. When BKMF is "1", characters specified for blinking by BLF are not displayed. (If the background color function is used, the background color is not disappeared.) Blinking specification unit: Character Blinking specification register (1 bit) *** BLF (bit 4 in ORDSN) "0" *** No blinking "1" *** Blinking Blinking master specification register (1 bit) *** BKMF (bit 5 in ORETC) "0" *** Disable blinking "1" *** Enable blinking (Characters whose BLF are set to "1" are not displayed.) Note: Regarding the extra dot of the left and/or right character by fringing function, it is not enabled as blink.
88CS34-183
2003-03-25
TMP88CS34/CP34
(5) Underline function Underline function is used to add a line under a display character. The underline is same color as that of character. Underline specification unit: Character/Line Underline enable register (Character unit) (1 bit) *** EUL (Bit 5 in ORDSN) "0" *** No underline "1" *** Underline Underline enable register (Line unit) (1 bit 12) *** EULAn (n: 1 to 8) (OREULA8), EULAn (n: 9 to 12) (OREULA12) Underline colors: 8 or 27 Underline color specification registers (3 bits) *** RDT, GDT, BDT (Bit 2 to 0 in ORDSN) (refer to Table 2.15.10) Note 1: To use the underline function, set both the underline enable register for underlining text in characters and that for underlining text in lines. If the former register (EUL) only is set, an underline is not displayed. Note 2: A color font underline can be displayed in colors set up using RDT, GDT, and RDT.
16
18 24
Character display area
6
Underline display area
EUL
0
EUL
1
Figure 2.14.34 Underline
88CS34-184
2003-03-25
TMP88CS34/CP34
(6) Solid space control Solid space control is used to display one column of solid space to the left and right of 32 columns. Solid space control is used to delete the Video signal in the areas where solid spaces are located in the original display page, then add color (raster color) to them. Solid space specification unit: line Solid space specification register (24 bits) For line 1 SOL11 and SOL10 (Bits 1 and 0 in ORSOL4) For line 2 SOL21 and SOL20 (Bits 3 and 2 in ORSOL4) . . . . . . For line 12 SOL121 and SOL120 (Bits 7 and 6 in ORSOL12) Solid space specification The solid space control functions as follows: SOLx1/SOLx0 (x "00" *** "01" *** "10" *** "11" *** 1 to 12) No solid space display Solid space display left for 32 columns Solid space display right for 32 columns Solid space display left and right for 32 columns
Solid space color specification registers (3 bits) *** RBDT, GBDT, BBDT (Bits 2 to 0 in ORBK) (Same color as that of background)
32 columns
Solid space (Left)
Solid space (Right)
Figure 2.14.35 Solid Space
88CS34-185
2003-03-25
TMP88CS34/CP34
(7) Slant function Slant function is used to slant characters for italics. Slant specification unit: Character Slant enable register (1 bit) *** SLNT (Bit 6 in ORDSN) "0" *** No slant "1" *** Slant Note 1: SLANT function is enabled each characters, and therefore, in case of using background function, this color of the Background is enable as slant. Regarding the extra dots of the left and/or right character by fringing function, it is not enabled as slant. Note 2: When a character is slanted in an area, which overlaps with the character field, the overlap is also slanted. Note 3: If slanting a character causes part of the character to get into the character field to the immediate right of the character, then this part is not displayed. Note 4: R, G, B, and Y are all slanted. Thus, if the Y signal is selected, a video signal is displayed above and to the left of the slant character. If the specified background color is black, setting YBLCS to 1 prevents the upper-left video signal for a slant character from being displayed. Note 5: When a character is slanted, the dot data to the immediate left of the character is also slanted. Note 6: Do not specify slanting for the color font.
The same color as that of the dot on the left is displayed.
When an entire character field (including its background) contains dots:
When the character field on the right does not contain a dot:
Figure 2.14.36 Slant
88CS34-186
2003-03-25
TMP88CS34/CP34
(8) Functions supporting PAL100/NTSC120 This LSI package supports the PAL (Phase Alternating Lines) 100 and NTSC (National Television System Community) 120 broadcasting systems. Figure 2.14.35 schematically shows the supported screen scanning method.
A
A
A
A
1st field 1
1st field 2
2nd field 1
2nd field 2
Figure 2.14.37 PAL100/NTSC120 Image Scanning Lines (Schematic Diagram) PAL100 support enable unit: Screen PAL100 support enable register (1 bit): EPAL100 (bit 5 in the ORDON register) PAL100 screen display start enable register (1 bit): PALTRG (bit 0 in the ORSTRG register) To support PAL100/NTSC120, follow this procedure. (a) To use PAL100/NTSC120, set the EPAL100 OSD control register (bit 5 in the ORDON register) to "1". (b) Read the phase detection results, PDF0 to PDF2, of the horizontal sync signal (HD) and the vertical sync signal (VD) (bits 6, 5, and 0 in the JESR jitter elimination status register) each time a VD interrupt occurs. (c) By reading the phase detection results PDF0 to PDF2, the phase of screen scanning is determined according to the detected field (1st or 2nd field). (d) Write PALTRG (bit 0 in the ORSTRG register) during the second cycle of the 2nd field (2nd field 2). Once PALTRG has been written, it becomes possible to support PAL100/NTSC120 for OSD display in the next field (1st field). Note 1: Use software to determine the write timing for PALTRG. Note 2: It is impossible to normally display the screen on the field of which PALTRG is written. Note 3: To read the phase detection results PDF0 to PDF2, write "1" to the JEEN jitter elimination control register (bit 2 in the JECR register) to enable the jitter elimination circuit.
88CS34-187
2003-03-25
TMP88CS34/CP34
2.14.6.8 OSD Control Registers Can not access all OSD control registers in any of read-modify-write instructions such as bit operation, etc.
0RHS1 (00F81H) 7 HS17 6 HS16 5 HS15 4 HS14 3 HS13 2 HS12 1 HS11 0 HS10 (Initial value: 0000 0000) Write only 2 VS12 1 VS11 VS19 0 VS10 VS18 (Initial value: 0000 0000) (Initial value: **** **00)
Horizontal display start position specification
ORVS1 (00F82H) (00F83H) ORVS2 (00F84H) (00F85H) ORVS3 (00F86H) (00F87H) ORVS4 (00F88H) (00F89H) ORVS5 (00F8AH) (00F8BH) ORVS6 (00F8CH) (00F8DH) ORVS7 (00F8EH) (00F8FH) ORVS8 (00F90H) (00F91H) ORVS9 (00F92H) (00F93H) ORVS10 (00F94H) (00F95H) ORVS11 (00F96H) (00F97H) ORVS12 (00F98H) (00F99H)
7 VS17
6 VS16
5 VS15
4 VS14
3 VS13
VS27
VS26
VS25
VS24
VS23
VS22
VS21 VS29
VS20 VS28
(Initial value: 0000 0000) (Initial value: **** **00)
VS37
VS36
VS35
VS34
VS33
VS32
VS31 VS39
VS30 VS38
(Initial value: 0000 0000) (Initial value: **** **00)
VS47
VS46
VS45
VS44
VS43
VS42
VS41 VS49
VS40 VS48
(Initial value: 0000 0000) (Initial value: **** **00)
VS57
VS56
VS55
VS54
VS53
VS52
VS51 VS59
VS50 VS58
(Initial value: 0000 0000) (Initial value: **** **00)
VS67
VS66
VS65
VS64
VS63
VS62
VS61 VS69
VS60 VS68
(Initial value: 0000 0000) (Initial value: **** **00)
VS77
VS76
VS75
VS74
VS73
VS72
VS71 VS79
VS70 VS78 VS80 VS88
(Initial value: 0000 0000) (Initial value: **** **00) (Initial value: 0000 0000) (Initial value: **** **00)
VS87
VS86
VS85
VS84
VS83
VS82
VS81 VS89
VS97
VS96
VS95
VS94
VS93
VS92
VS91 VS99
VS90 VS98
(Initial value: 0000 0000) (Initial value: **** **00)
VS107
VS106
VS105
VS104
VS103
VS102
VS101 VS109
VS100 VS108
(Initial value: 0000 0000) (Initial value: **** **00)
VS117
VS116
VS115
VS114
VS113
VS112
VS111 VS119
VS110 VS118
(Initial value: 0000 0000) (Initial value: **** **00)
VS127
VS126
VS125
VS124
VS123
VS122
VS121 VS129
VS120 VS128
(Initial value: 0000 0000) (Initial value: **** **00) Write only (n: 1 to 12)
VSn8 to 0
Vertical display start position for line n
Note 1:
If display lines are overlapped each other, previous display line is enabled and next line is disabled. Set the vertical display start position not to overlap display lines.
Note 2:
Transfer the contents of vertical display start position registers into OSD circuit before a position of the scanning line coincides with their own vertical display start position.
88CS34-188
2003-03-25
TMP88CS34/CP34
ORCS4 (00F9AH) ORCS8 (00F9BH) ORCS12 (00F9CH)
7 CS4 CS8 CS12
6
5 CS3 CS7 CS11
4
3 CS2 CS6 CS10
2
1 CS1 CS5 CS9 Display off Large size Middle size Small size
0 (Initial value: 0000 0000) (Initial value: 0000 0000) (Initial value: 0000 0000)
CSn
Character size and display on/off for line n
00: 01: 10: 11:
Write only (n: 1 to 12)
OREULA8 (00F9DH) OREULA12 (00F9EH)
EULA8
EULA7
EULA6
EULA5
EULA4
EULA3
EULA2
EULA1
(Initial value: 0000 0000) (Initial value: **** 0000)
EULA12 EULA11 EULA10 EULA9 EULAn Underline for display line for line n 0: 1: Display off Display on
(n: 1 to 12) OREFR8 (00F9FH) OREFR12 (00FA0H) 7 EFR8 6 EFR7 5 EFR6 4 EFR5 3 EFR4 EFR12 EFRn Fringing enable specification register for line n 2 EFR3 EFR11 0: 1: 1 EFR2 EFR10 0 EFR1 EFR9 (Initial value: 0000 0000) (Initial value: **** 0000) Write only (n: 1 to 12) ORSLO4 (00FA2H) ORSLO8 (00FA3H) ORSLO12 (00FA4H)
Disable fringing Enable fringing
SLO4 SLO8 SLO12
SLO3 SLO7 SLO11
SLO2 SLO6 SLO10 00: 01: 10: 11:
SLO1 SLO5 SLO9
(Initial value: 0000 0000) (Initial value: 0000 0000) (Initial value: 0000 0000)
SLOn
Solid space for line n
No solid space display Solid space display left Solid space display right Solid space display left and right
Write only (n: 0 to 12)
88CS34-189
2003-03-25
TMP88CS34/CP34
ORBK (00FA5H)
7
6 RBDT
5 GBDT
4 BBDT
3
2 RFDT
1 GFDT
0 BFDT (Initial value: 0000 0000)
RBDT/ GBDT/ BBDT
Background color select
000: Setting color of ORCPT0 001: Setting color of ORCPT1 010: Setting color of ORCPT2 011: Setting color of ORCPT3 000: Setting color of ORCPT4 101: Setting color of ORCPT5 110: Setting color of ORCPT6 111: Setting color of ORCPT7 000: Setting color of ORCPT0 001: Setting color of ORCPT1 010: Setting color of ORCPT2 011: Setting color of ORCPT3 000: Setting color of ORCPT4 101: Setting color of ORCPT5 110: Setting color of ORCPT6 111: Setting color of ORCPT7
Write only
RFDT/ GFDT/ BFDT
Fringing color select
88CS34-190
2003-03-25
TMP88CS34/CP34
ORACL (00FA6H)
7
6
5
4
3
2
1
0 (Initial value: 0000 0000)
PISEL2 ACLR2 ACLG2
ACLB2 PISEL1 ACLR1
ACLG1 ACLB1
ACLR2/ ACLG2/ ACLB2
Area 2 plane color select
000: Setting color of ORCPT0 001: Setting color of ORCPT1 010: Setting color of ORCPT2 011: Setting color of ORCPT3 000: Setting color of ORCPT4 101: Setting color of ORCPT5 110: Setting color of ORCPT6 111: Setting color of ORCPT7 000: Setting color of ORCPT0 001: Setting color of ORCPT1 010: Setting color of ORCPT2 011: Setting color of ORCPT3 000: Setting color of ORCPT4 101: Setting color of ORCPT5 110: Setting color of ORCPT6 111: Setting color of ORCPT7 0: Not assign half transparency for area 2 plane 1: Assign half transparency for area 2 plane 0: Not assign half transparency for area 1 plane 1: Assign half transparency for area 1 plane Write only
ACLR1/ ACLG1/ ACLB1
Area 1 plane color select
PISEL2 PISEL1
88CS34-191
2003-03-25
TMP88CS34/CP34
ORIV (00FBBH)
7
6
5 YBLII
4 RGBII
3 YIV
2 BLIV
1 RGBIV
0 IIV (Initial value: 0000 0000)
VDPOL HDPOL VDPOL HDPOL YBLII RGBII YIV BLIV RGBIV IIV
0: Non-invert input signal 1: Invert input signal 0: Non-invert input signal HD input polarity select 1: Invert input signal 0: Active high Y/BLIN input polarity select 1: Active low 0: Active high RIN, GIN, BIN input polarity select 1: Active low 0: Active high Y output polarity select 1: Active low 0: Active high BL output polarity select 1: Active low 0: Active high R, G, B output polarity select 1: Active low 0: Active high I output polarity select 1: Active low
VD input polarity select
Write only
ORDMA (00024H) (00025H)
7 DMA7
6 DMA6
5 DMA5
4 DMA4
3 DMA3
2 DMA2
1 DMA1
0 DMA0 DMA8 (Initial value: 0000 0000) (Initial value: **** ***0) Write only (n: 0 to 8)
DMAn
Display memory address
Note:
It is necessary to write all bits of display memory address, writng DMA7 to DMA0 after DMA8, when writing display address.
6 SLNT 5 EUL 4 BLF 3 ECBKD 2 RDT 1 GDT 0 BDT (Initial value: **** ****)
ORDSN (0001DH)
7
SLNT EUL BLF ECBKD
Slant enable specification register Underline enable specification register Blinking enable specification register Character-specific background on/off specification
0: Disable slant 1: Enable slant 0: Disable underline 1: Enable underline 0: Disable blinking 1: Enable blinking 0: Disable backgournd color display 1: Enable backgournd color display 000: Setting color of ORCPT0 001: Setting color of ORCPT1 010: Setting color of ORCPT2 011: Setting color of ORCPT3 000: Setting color of ORCPT4 101: Setting color of ORCPT5 110: Setting color of ORCPT6 111: Setting color of ORCPT7 Read/ Write
RDT/ GDT/ BDT
Character color select
Note:
To display a background color, write "1" to EBKGD (bit 7 in the ORRCL register) to enable the background function enable register for the entire screen.
88CS34-192
2003-03-25
TMP88CS34/CP34
ORCRA (0001EH) (0001FH)
7 CRA7
6 CRA6
5 CRA5
4 CRA4
3 CRA3
2 CRA2
1 CRA1
0 CRA0 CRA8 (Initial value: **** ****) (Initial value: **** ****) Read/ Write (n: 0 to 8)
CRAn
Character code
Note: Write or read CRA7 to CRA0 after write or read CRA8.
ORWVSH (00FBCH) (00FBDH) WVSLn Window upper limit position 7 6 5 4 3 2 1 0 (Initial value: 0000 0000) (Initial value: **** **00) Write only (n: 0 to 9) ORWVSL (00FBEH) (00FBFH) WVSLn Window lower limit position 7 6 5 4 3 2 1 0 (Initial value: 0000 0000) (Initial value: **** **00) Write only (n: 0 to 9) ORDON (00F80H) 7 6 5 4 3 2 1 EWDW 0 DON (Initial value: **00 0000)
WVSH7 WVSH6 WVSH5 WVSH4 WVSH3 WVSH2 WVSH1 WVSH0 WVSH9 WVSH8
WVSL7 WVSL6 WVSL5 WVSL4 WVSL3 WVSL2 WVSL1 WVSL0 WVSL9 WVSL8
EPAL100 ROMACH ECHDSN RGWR
EPAL100
PAL100 mode specification register
0: 1: 0:
PAL100 mode disable PAL100 mode enable 383 monochrome font characters 96 color font characters 447 monochrome font characters 64 color font characters Character-specific background color setting off Character-specific background color setting on (Initial setting) Written data is transferred to the OSD circuit (cleared to "0" after the transfer). Window specification off Window specification on Display off Display on Read/ Write
Monochrome/color font area ROMACH switching register Character-specific background color setting on/off specification register
1:
ECHDSN
0: 1:
RGWR
0: Data transfer control OSD register 1: Window enable specification register Display on/off specification register 0: 1: 0: 1:
EWDW DON
Note 1: *: Don't care Note 2: All OSD control registers cannot use the read-modify-write instructions. (Bit manipulation instructions such as SET, CLR, etc. and logical operation such as AND, OR, etc.)
88CS34-193
2003-03-25
TMP88CS34/CP34
ORRCL (00FA7H)
7 EBKGD
6 EXBL
5 AON2
4 AON1
3
2 RCLR
1 RCLG
0 RCLB (Initial value: 0000 *000)
EBKGD EXBL AON2 AON1
Background function enable specification register Full-raster blanking enable specification register Area 2 plane display enable specification register Area 1 plane display enable specification register
0: No background function 1: Background function enable 0: No Full-raster blanking 1: Full-raster blanking 0: No area 2 plane display 1: Area 2 plane display enable 0: No area 1 plane display 1: Area 1 plane display enable 000: Setting color of ORCPT0 001: Setting color of ORCPT1 010: Setting color of ORCPT2 011: Setting color of ORCPT3 000: Setting color of ORCPT4 101: Setting color of ORCPT5 110: Setting color of ORCPT6 111: Setting color of ORCPT7 Write only
RCLR/ RCLG/ RCLB
Raster plane color select
88CS34-194
2003-03-25
TMP88CS34/CP34
ORAHS1 (00FA8H) (00FA9H) ORAHE1 (00FAAH) (00FABH)
7 AHS17
6 AHS16
5 AHS15
4 AHS14
3 AHS13
2 AHS12
1 AHS11
0 AHS10 AHS18 (Initial value: 0000 0000) (Initial value: **** ***0)
AHE17
AHE16
AHE15
AHE14
AHE13
AHE12
AHE11
AHE10 AHE18
(Initial value: 0000 0000) (Initial value: **** ***0) Write only (n: 0 to 8)
AHS1n AHE1n
Horizontal start point for area 1 plane Horizontal end point for area 1 plane
ORAVS1 (00FACH) (00FADH) ORAVE1 (00FAEH) (00FAFH)
AVS17
AVS16
AVS15
AVS14
AVS13
AVS12
AVS11 AVS19
AVS10 AVS18
(Initial value: 0000 0000) (Initial value: **** **00)
AVE17
AVE16
AVE15
AVE14
AVE13
AVE12
AVE11 AVE19
AVE10 AVE18
(Initial value: 0000 0000) (Initial value: **** **00) Write only (n: 0 to 9)
AVS1n AVE1n
Vertical start point for area 1 plane Vertical end point for area 1 plane
ORAHS2 (00FB0H) (00FB1H) ORAHE2 (00FB2H) (00FB3H)
AHS27
AHS26
AHS25
AHS24
AHS23
AHS22
AHS21
AHS20 AHS28
AHE27
AHE26
AHE25
AHE24
AHE23
AHE22
AHE21
AHE20 AHE28
(Initial value: 0000 0000) (Initial value: **** ***0) Write only (n: 0 to 8)
AHS2n AHE2n
Horizontal start point for area 2 plane Horizontal end point for area 2 plane
ORAVS2 (00FB4H) (00FB5H) ORAVE2 (00FB6H) (00FB7H)
AVS27
AVS26
AVS25
AVS24
AVS23
AVS22
AVS21 AVS29
AVS20 AVS28
(Initial value: 0000 0000) (Initial value: **** **00)
AVE27
AVE26
AVE25
AVE24
AVE23
AVE22
AVE21 AVE29
AVE20 AVE28
(Initial value: 0000 0000) (Initial value: **** **00) Write only (n: 0 to 9)
AVS2n AVE2n
Vertical start point for area 2 plane Vertical end point for area 2 plane
88CS34-195
2003-03-25
TMP88CS34/CP34
ORP6S (00FBAH)
7 P67S P67S to P64S PIDS YBLCS
6 P66S
5 P65S
4 P64S
3 PIDS
2 YBLCS
1 MPXS
0 (Initial value: 0000 0000)
P6 port output select I pin output select Y/BL signal select
MPXS
R, G, B, Y/BL signal select
0: R, G, B, Y/BL signal output 1: Port contents output 0: I signal output 1: Port contents output 0: Y signal output 1: BL signal output 00: Simultaneous output (Signal from the OSD circuit has higher priority.) 01: Output of signal from internal OSD circuit 10: Output of signal from externally input 11: Simultaneous output (Externally input signal has higher priority.) 3 "0" 2 MFYWR 1 MBK 0 RDWRV (Initial value: 0000 0000)
Write only
ORETC (00FB8H)
7 VDSMD VDSMD BKMF ESMZ MFYWR
6 "0"
5 BKMF
4 ESMZ
Scan mode select Blinking master Smoothing enable specification register Display memory read mode select Display memory bank switching Read/write mode select at normal mode
0: Normal mode 1: Double scan mode 0: Double blinking 1: Enable blinking 0: Disable smoothing 1: Enable smoothing 0: Normal mode 1: Read-modify-write-mode 0: Access to either character code or character display options 1: Access both character code and character display option 0: Data write mode for display memory 1: Data read mode for display memory Write only
MBK
RDWRV
Note:
Clear "0" to bit 6 and 3 in ORETC.
88CS34-196
2003-03-25
TMP88CS34/CP34
ORIRC (00FB9H)
7
6
5
4 SDV
3
2 ISDC
1
0 (Initial value: ***0 0000)
SVD
Interrupt source select
ISDC
Interrupt generation line select
0: Interrupt request by ISDC value 1: Interrupt request at falling edge of VD signal When the line display of the ISDC value ends (with the falling edge of HD signal) while SVD 0, interrupt request is generated. 0000: Request interrupt when display of low-order 4 bits "0000" of DCTR ends. 0001: Low-order 4 bits "0001" of DCTR 0010: Low-order 4 bits "0010" of DCTR 0011: Low-order 4 bits "0011" of DCTR 0100: Low-order 4 bits "0100" of DCTR 0101: Low-order 4 bits "0101" of DCTR 0110: Low-order 4 bits "0110" of DCTR 0111: Low-order 4 bits "0111" of DCTR 1000: Low-order 4 bits "1000" of DCTR 1001: Low-order 4 bits "1001" of DCTR 1010: Low-order 4 bits "1010" of DCTR 1011: Low-order 4 bits "1011" of DCTR 1100: Low-order 4 bits "1100" of DCTR 1101: Low-order 4 bits "1101" of DCTR 1110: Low-order 4 bits "1110" of DCTR 1111: Low-order 4 bits "1111" of DCTR
Write only
ORIRC (00FB9H)
DCTR
(Initial value: **** 0000)
DCTR
Display line counter
0000: No line display or when the display of the 16th line ends. 0001: 1st line display ends. 0010: 2nd line display ends. 0011: 3rd line display ends. 0100: 4th line display ends. 0101: 5th line display ends. 0110: 6th line display ends. 0111: 7th line display ends. 1000: 8th line display ends. 1001: 9th line display ends. 1010: 10th line display ends. 1011: 11th line display ends. 1100: 12th line display ends. 1101: 13th line display ends. 1110: 14th line display ends. 1111: 15th line display ends.
Read only
Note:
The display line counter also increments when a line with all blank data or a line with display off is specified. If display lines are overlapped each other, previous display line is enabled and next line is disabled. At this time, the display line counter also increments.
88CS34-197
2003-03-25
TMP88CS34/CP34
ORDCSC (00FC4H) (00FC5H)
7
6
5
4
3
2
1
0
DCSC8 DCSC7 DCSC6 DCSC5 DCSC4 DCSC3 DCSC2 DCSC1 (Initial value: 0000 0000) DCSC12 CDSC11 CDSC10 CDSC9 (Initial value: **** 0000) n: Double-height specification for row n n: 1 to 12 Note: 0: Display a medium-size character when medium-size character display is specified. 1: Display a double-height character when medium-size character display is specified. 1 to 12) in the ORCSm (m 1 to 12).
DCSCn
Write only
To display double-height characters, write "10" to CSn (n
4, 8, 12) register,
specify the medium character size, and write "1" to DCSCn (n 7 ORCPT0 (00FC6H) ORCPT1 (00FC7H) ORCPT2 (00FC8H) ORCPT3 (00FC9H) ORCPT4 (00FCAH) ORCPT5 (00FCBH) ORCPT6 (00FCCH) ORCPT7 (00FCDH)
CPT0MD1
6 Fixed at 0 6
5
4
3
2
1
0 (Initial value: 0000 0000)
CPT0R1 CPT0R0 CPT0G1 CPT0G0 CPT0B1 CPT0B0
7
5
4
3
2
1
0 (Initial value: **00 0000)
CPT1R1 CPT1R0 CPT1G1 CPT1G0 CPT1B1 CPT1B0 7 6 5 4 3 2 1 0
CPT2R1 CPT2R0 CPT2G1 CPT2G0 CPT2B1 CPT2B0 7 6 5 4 3 2 1 0
(Initial value: **00 0000)
CPT3R1 CPT3R0 CPT3G1 CPT3G0 CPT3B1 CPT3B0 7 6 5 4 3 2 1 0
(Initial value: **00 0000)
CPT4R1 CPT4R0 CPT4G1 CPT4G0 CPT4B1 CPT4B0 7 6 5 4 3 2 1 0
(Initial value: **00 0000)
CPT5R1 CPT5R0 CPT5G1 CPT5G0 CPT5B1 CPT5B0 7 6 5 4 3 2 1 0
(Initial value: **00 0000)
CPT6R1 CPT6R0 CPT6G1 CPT6G0 CPT6B1 CPT6B0 7 6 5 4 3 2 1 0
(Initial value: **00 0000)
CPT7R1 CPT7R0 CPT7G1 CPT7G0 CPT7B1 CPT7B0 27-color mode CPT0MD1 specification register 0: 8-color mode 1: 27-color mode
(Initial value: **00 0000)
Write only
CPTOMD1 = 0 CPTxR0 CPTxR1 R luminance specification register G luminance specification register B luminance specification register 6 5 CRTxR1 CRTxR1 CRTxR1 CRTxR1 0, CRTxR0 0, CRTxR0 1, CRTxR0 1, CRTxR0 0: No output 1: Light red 0: Light red 1: Light red CRTxR1 CRTxR1 CRTxR1 CRTxR1
CPTOMD1 = 1 0, CRTxR0 0, CRTxR0 1, CRTxR0 1, CRTxR0 0: No output 1: Dark red 0: Dark red 1: Light red Write only
CPTxG0 CPTxG1
CRTxG1 0, CRTxG0 0: No output CRTxG1 0, CRTxG0 1: Light green CRTxG1 1, CRTxG0 0: Light green CRTxG1 1, CRTxG0 1: Light green CRTxB1 CRTxB1 CRTxB1 CRTxB1 4 0, CRTxB0 0, CRTxB0 1, CRTxB0 1, CRTxB0 3 2 0: No output 1: Light blue 0: Light blue 1: Light blue 1
CRTxG1 0, CRTxG0 0: No output CRTxG1 0, CRTxG0 1: Dark green CRTxG1 1, CRTxG0 0: Dark green CRTxG1 1, CRTxG0 1: Light green CRTxB1 CRTxB1 CRTxB1 CRTxB1 0 0, CRTxB0 0, CRTxB0 1, CRTxB0 1, CRTxB0 0: No output 1: Dark blue 0: Dark blue 1: Light blue
CPTxB0 CPTxB1
ORSTRG1 (00FCEH)
7
PALTRG PAL100 mode trigger start register 0: PAL trigger stop 1: PAL trigger start
(Initial value: **** ***0)
PALRG
Write only
88CS34-198
2003-03-25
TMP88CS34/CP34
OSD Control Register List (1/3)
Register Address Register Name Bit 7 Bit 6 Bit 5 Register bit configuration Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 When ECHDSN = 0 SLNT 1: Slant enable, 0: Slant disable EUL = 1: Underline display on, 0: Underline display off When ECHDSN 0001D ORDSN SLNT EUL BLF ECBKD RDT GDT BDT 1 R/W SLNT: Background color red EUL: Background color green BLF 1: Blinking enable, 0: Blinking disable ECBKD 1:Character background color display enable, Character background color display disable 0001E 0001F 00024 00025 ORDMA DMA7 DMA6 DMA5 DMA4 DMA3 DMA2 DMA1 ORCRA CRA7 CRA6 CRA5 CRA4 CRA3 CRA2 CRA1 CRA0 CRA8 DMA0 DMA8 EPAL100 1: PAL100/NTSC120 select, 0: Other DMAx: Display memory address setting (x: 0 to 8) W CRAx: Character code (x: 0 to 8) R/W Bit contents R/W
ROMACH: Select font number (mono font/color font) 1: 447 mono font character/64 color font character, 0: 383 mono font character/96 color font character 00F80 ORDON EPAL100 ROMACH ECHDSN RGWR EWDW DON ECHDSN 1: Bit 6 and 5 in ORDSN is changed to character background color, 0: Bit 6 and 5 in ORDSN is character ornamentation RGWR: Writing data transfer control bit EWDW 1: Window function enable, 0: Window function disable DON 00F81 00F82 00F83 00F84 00F85 00F86 00F87 00F88 00F89 00F8A 00F8B 00F8C 00F8D 00F8E 00F8F 00F90 00F91 00F92 00F93 00F94 00F95 00F96 00F97 00F98 00F99 00F9A 00F9B 00F9C 00F9D 00F9E 00F9F 00FA0 ORCS4 ORCS8 ORCS12 OREULA8 OREULA12 OREFR8 OREFR12 EFR8 EFR7 EFR6 EFR5 CS4 CS8 CS12 EULA8 EULA7 EULA6 CS3 CS7 CS11 EULA5 CS2 CS6 CS10 EULA4 EULA12 EFR4 EFR12 EULA3 ORVS12 VS127 VS126 VS125 VS124 VS123 VS122 ORVS11 VS117 VS116 VS115 VS114 VS113 VS112 ORVS10 VS107 VS106 VS105 VS104 VS103 VS102 ORVS9 VS97 VS96 VS95 VS94 VS93 VS92 ORVS8 VS87 VS86 VS58 VS84 VS83 VS82 ORVS7 VS77 VS76 VS75 VS74 VS73 VS72 ORVS6 VS67 VS66 VS65 VS64 VS63 VS62 ORVS5 VS57 VS56 VS55 VS54 VS53 VS52 ORVS4 VS47 VS46 VS45 VS44 VS43 VS42 ORVS3 VS37 VS36 VS35 VS34 VS33 VS32 ORVS2 VS27 VS26 VS25 VS24 VS23 VS22 ORHS1 ORVS1 HS17 VS17 HS16 VS16 HS15 VS15 HS14 VS14 HS13 VS13 HS12 VS12 HS11 VS11 VS19 VS21 VS29 VS31 VS39 VS41 VS49 VS51 VS59 VS61 VS69 VS71 VS79 VS81 VS89 VS91 VS99 VS101 VS109 VS111 VS119 VS121 VS129 HS10 VS10 VS18 VS20 VS28 VS30 VS38 VS40 VS48 VS50 VS58 VS60 VS68 VS70 VS78 VS80 VS88 VS90 VS98 VS100 VS108 VS100 VS118 VS120 VS128 CS1 CS5 CS9 EULA2 EULA1 EULA9 EFR1 EFR9 EFRn: Fringing setting for line n (n: 0 to 12) W CSn: Character size (n: 1 to 12) 00: Display off 10: Middle size 01: Large size 11: Small size EULAn: Underline display setting for line n (n: 0 to 12) W W VS120 to VS129:Code vertical display potision setting W VS110 to VS119:Code vertical display potision setting W VS100 to VS109:Code vertical display potision setting W VS99 to VS90: Code vertical display potision setting W VS89 to VS80: Code vertical display potision setting W VS79 to VS70: Code vertical display potision setting W VS69 to VS60: Code vertical display potision setting W VS59 to VS50: Code vertical display potision setting W VS49 to VS40: Code vertical display potision setting W VS39 to VS30: Code vertical display potision setting W VS29 to VS20: Code vertical display potision setting W 1: OSD display ON, 0: OSD display OFF W W R/W
HS17 to HS10: Code horizontal display base position setting VS19 to VS10: Code vertical display potision setting
EULA11 EULA10 EFR3 EFR11 EFR2 EFR10
88CS34-199
2003-03-25
TMP88CS34/CP34
OSD Control Register List (2/3)
Register Address 00FA2 00FA3 00FA4 00FA5 Register Name ORSOL4 ORSOL8 ORSOL12 ORBK Bit 7 SOL4 SOL8 SOL12 RBDT Bit 6 Bit 5 SOL3 SOL7 SOL11 GBDT BBDT Register bit configuration Bit 4 Bit 3 SOL2 SOL6 SOL10 RFDT Bit 2 Bit 1 Bit 0 SOL1 SOL5 SOL9 GFDT BFDT SOLn: Solid space display setting for line n (n; 0 to 12) 00: No solid space 01: Left 10: Right 11: Left and right W W Bit contents R/W
RBDT, GBDT, BBDT: Background color setting ACLR2/ACLG2/ACLB2: Area 2 plane color
00FA6
ORACL
PISEL2
ACLR2
ACLG2
ACLB2
PISEL1
ACLR1
ACLG1
ACLB1
ACLR1/ACLG1/ACLB1: Area 1 plane color PISEL2: Set half transparency for area 2 plane PISEL1: Set half transparency for area 1 plane EBKGD: Background function EXBL: Full-rasterblanking
W
00FA7
ORRCL
EBKGD
EXBL
AON2
AON1
RCLR
RCLG
RCLB
AON2: Area 2 plane display AON1: Area 1 plane display RCLR/RCLG/RCLB:Raster plane color
00FA8 00FA9 00FAA 00FAB 00FAC 00FAD 00FAE 00FAF 00FB0 00FB1 00FB2 00FB3 00FB4 00FB5 00FB6 00FB7
ORAHS1
AHS17
AHS16
AHS15
AHS14
AHS13
AHS12
AHS11
AHS10 AHS18
AHS1x: Area 1 plane horizonatal start position (x: 0 to 8) AHE1x: Area 1 plane horizonatal end position (x: 0 to 8) AVS1x: Area 1 plane vertical start position (x: 0 to 8)
ORAHE1
AHE17
AHE16
AHE15
AHE14
AHE13
AHE12
AHE11
AHE10 AHE18
ORAVS1
AVS17
AVS16
AVS15
AVS14
AVS13
AVS12
AVS11 AVS19
AVS10 AVS18 AVE10 AVE18 AHS20 AHS28
ORAVE1
AVE17
AVE16
AVE15
AVE14
AVE13
AVE12
AVE11 AVE19
AVE1x: Area 1 plane vertical end position (x: 0 to 8) AHS2x: Area 2 plane horizonatal start position (x: 0 to 8) AHE2x: Area 2 plane horizonatal end position (x: 0 to 8) AVS2x: Area 2 plane vertical start position (x: 0 to 8) AVE2x: Area 2 plane vertical end position (x: 0 to 8) VDSMD: Scan mode select BKMF: Blinking master ESMZ: Smoothing MFYWR: Display memory read mode select MBK: Display memory bank switching select RDWRV: Read/write mode select normal mode
ORAHS2
AHS27
AHS26
AHS25
AHS24
AHS23
AHS22
AHS21
ORAHE2
AHE27
AHE26
AHE25
AHE24
AHE23
AHE22
AHE21
AHE20 AHE28
ORAVS2
AVS27
AVS26
AVS25
AVS24
AVS23
AVS22
AVS21 AVS29
AVS20 AVS28 AVE20 AVE28
ORAVE2
AVE27
AVE26
AVE25
AVE24
AVE23
AVE22
AVE21 AVE29
00FB8
ORETC
VDSMD
0
BKMF
ESMZ
0
MFYWR
MBK
RDWRV
W
00FB9 00FB9
ORIRC ORIRC
SVD
ISDC DCTR
SVD: Interrupt source select ISDC: Interrupt generation line select DCTR:Display line counter P6xS: P6 port output select (x:4 to 7)
W R
00FBA
ORP6S
P67S
P66S
P65S
P64S
PIDS
YBLCS
MPX
PIDS: I pin output select YBLCS: Y/BL signal select MPXS: R, G, B, Y/BL signal select HDPOL: VD input polarity select HDPOL: HD input polarity select YBLII: Y/BLIN input polarity select RGBII: RIN, GIN, BIN input polarity select Y/V: Y Output polarity select BLIV: BL output polarity select RGBIV: R, G, B output polarity select IIV: I pin output polarity select
W
00FBB
ORIV
VDPOL
HDPOL
YBLII
RGBII
YIV
BLIV
RGBIV
IIV
W
00FBC 00FBD 00FBE 00FBF 00FC2 00FC3 00FC4 00FC5
ORWVSH
WVSH7
WVSH6
WVSH5
WVSH4
WVSH3
WVSH2
WVSH1 WVSH9
WVSH0 WVSH8 WVSL0 WVSL8 CCD1 CCD9 DCSC1
WVSHx: Window upper limit position (x: 0 to 9)
W
ORWVSL
WVSL7
WVSL6
WVSL5
WVSL4
WVSL3
WVSL2
WVSL1 WVSL9
WVSLx: Window lower limit position (x: 0 to 9) CCDx: Horizontal 16 dot and vertical 26 dot display at small size character (x: 0 to 12) DCSCx: Double height display (x: 0 to 12)
W
ORCCD
CCD8
CCD7
CCD6
CCD5
CCD4 CCD12
CCD3 CCD11 DCSC3 DCSC11
CCD2 CCD10 DCSC2
W
DCSC8 ORDCSC
DCSC7
DCSC6
DCSC5
DCSC4 DCSC12
W
DCSC10 DCSC9
88CS34-200
2003-03-25
TMP88CS34/CP34
OSD Control Register List (3/3)
Register Address Register Name Bit 7 Bit 6 Bit 5 Register bit configuration Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Color palette composition register 0 CPT1MD1: OSD color select register (x: 1, 2) 00FC6 ORCPT0 CPT0MD1 0 CPT0R1 CPT0R0 CPT0G1 CPT0G0 CPT0B1 CPT0B0 CPT1MD1 CPT1MD1 00FC7 00FC8 00FC9 00FCA 00FCB 00FCC 00FCD 00FCE ORCPT1 ORCPT2 ORCPT3 ORCPT4 ORCPT5 ORCPT6 ORCPT7 ORSTRG CPT1R1 CPT2R1 CPT3R1 CPT4R1 CPT5R1 CPT6R1 CPT7R1 CPT1R0 CPT2R0 CPT3R0 CPT4R0 CPT5R0 CPT6R0 CPT7R0 CPT1G1 CPT2G1 CPT3G1 CPT4G1 CPT5G1 CPT6G1 CPT7G1 CPT1G0 CPT1B1 CPT2G0 CPT2B1 CPT3G0 CPT3B1 CPT4G0 CPT4B1 CPT5G0 CPT5B1 CPT6G0 CPT6B1 CPT7G0 CPT7B1 0: 27-color select mode 1: 8-color select mode W W W W W W W W W Bit contents R/W
CPT1B0 Color palette composition register 1 CPT2B0 Color palette composition register 2 CPT3B0 Color palette composition register 3 CPT4B0 Color palette composition register 4 CPT5B0 Color palette composition register 5 CPT6B0 Color palette composition register 6 CPT7B0 Color palette composition register 7 PALTRG PAL100/NTSC120 start trigger
Note 1: Except the meshed registers are changed by RGWR. Note 2: Only lower 2 bits of the register in address 00F80H are changed by RGWR (The register in address 00F80H must not be used with any of the read-modify-write instructions as SET, CLR, etc.).
88CS34-201
2003-03-25
TMP88CS34/CP34
2.15 Jitter Elimination Circuit
The TMP88CS34/CP34 has a built-in jitter elimination circuit which maintains the vertical stability of the OSD even when input of the vertical signal fluctuates. And the field decision information for the OSD circuit is detected by using jitter elimination circuit.
2.15.1
Configuration
Jitter removal status register Phase detect signal PDF [2:0] Field decision circuit JRMSR AY B S Previous field decision signal
HD (P70)
VD (P71)
HD / VD
Edge detect circuit
Delay value setting circuit
Internal VD signal output control circuit
A B Y
VD
(To OSD circuit)
VDSEL VD signal delay value measuring circuit AFLD JECR Jitter elimination control register JEEN
fc/2
Figure 2.15.1 Jitter Elimination Circuit
88CS34-202
2003-03-25
TMP88CS34/CP34
2.15.2 Control
Jitter elimination circuit is controlled by the jitter elimination control register (JECR).
Jitter elimination control register 7 6 JECR (00FE4H) VDSEL AFLD JEEN Note 1: Note 2: Note 3: VD select Automatic field decision Jitter elimination enable specification
5
4 VDSEL
3 AFLD
2 JEEN 0: 1: 0: 1: 0: 1:
1 "0"
0 "0" (Initial value: ***0 0000)
VD from P71 VD from jitter elimination circuit Automatic field decision disabled Automatic field decision enabled Jitter elimination disabled Jitter elimination enabled
Write only
Clear the AFLD to "0" to disable jitter elimination circuit. Always clear "0" to bit 1 and 0 of JECR. Clear "0" to AFLD and VDSEL if there is no phase shift in the vertical and horizontal sync. signals every other time, such as with non-interlaced TV.
Note 4: Note 5: Note 6:
*: Don't care Setting JEEN to "0", OSD display is only 2nd field. Setting AFLD to "0", OSD display is only 2nd field.
Jitter elimination status register 7 6 JESR (00FE5H) FDSF PDF1
5 PDF0
4
3
2
1
0 PDF2 (Initial value: 0*** ****)
FDSF
Field detect status flag
PDF2, 1, 0 Phase detect flag between HD and VD
A position of a scanning line exists in the field which has a second display dot of character on an interlace TV screen. 1: A position of a scanning line exists in the field which has a first display dot of character on an interlace TV screen. Read 000: Phase 0 only 001: Phase 1 010: Phase 2 011: Phase 3 100: Phase 4 101: Phase 5 110: Phase 6 111: Phase 7
0:
Note 1: Note 2: Note 3:
FDSF is different from the 1st and the 2nd field. It is a unique field decided for OSD display. *: Don't care
HD
VD
Phase 7
Phase 0
Phase 1
Phase 2
Phase 3
Phase 4
Phase 5
Phase 6
Phase 7
Phase 0
Figure 2.15.2 Jitter Elimination Control Register and Jitter Elimination Status Register
2.15.3 Jitter Elimination Mode
The jitter elimination circuit is to identify the phase of the falling edges of the external / 1/4HD, the jitter is automatically eliminated and internal VD signal is set to the stable location. This function is enabled by setting JEEN (bit2 in JECR) in the jitter elimination control register to "1".
VD signal and HD signal. When VD signal is falling within HD signal falling
88CS34-203
2003-03-25
TMP88CS34/CP34
2.15.4 Auto Field Line Decision
The internal vertical and horizontal sync. signals corrected by the jitter elimination circuit generate the field line decision signals used in the OSD. The OSD display in normal mode Type A) When the OSD circuit is used on the TV system which has a phase shift in the vertical and horizontal sync. Signals every other filed such as the interlace TV, enable jitter elimination circuit and set "1" to AFLD and VDSEL. At this time, the field lines which have first and second display dot of character are displayed. When the OSD circuit is used on the TV system which has no phase shift in the vertical and horizontal sync. Signals every other filed such as the non-interlace TV, enable jitter elimination circuit and clear "0" to AFLD and VDSEL. At this time, the field line which has a second display dot of character is only displayed.
Type B)
The OSD display in double scan mode Type C) Disable jitter elimination circuit and clear "0" to AFLD and VDSEL. At this time, the field lines which have first and second display dot of character are displayed.
(2) The field line which has a second display dot of character
(1) The field line which has a first display dot of character
Scanning system Type A Type B Type C
Register VDSEL VDSEL VDSEL 1, AFLD 0, AFLD 0, AFLD 1 0 0
Display (1) and (2) (2) (1) and (2)
Figure 2.15.3 Relation with Field Line and VDSEL, AFLD
88CS34-204
2003-03-25
TMP88CS34/CP34
Input/Output Circuit
(1) Control pins The input/output circuitries of the TMP88CS34/CP34 control pins are shown below.
Control Pin I/O Osc. enable VDD Input/Output Circuitry fc Rf VDD Remarks Resonator connecting pins (high-frequency) Rf 1.2 M (typ.) RO 0.5 k (typ.)
XIN XOUT
I/O
RO
XIN
XOUT VDD RIN R Sink open drain output Hysteresis input Pull-up register RIN 220 M (typ.) R 1 k (typ.)
RESET
I/O
Address-trap-reset Watchdog-timer-reset System-clock-reset
VDD
STOP / INT5
Hysteresis input R 1k (typ.)
(P20)
Input R P20/ STOP / INT5 Pull-down register VDD R RIN 70 k (typ.) R 1 k (typ.) RIN
TEST
Input
Osc. enable VDD I/O
fc Rf VDD
Pin for connecting a resonator for on-screen display Rf 1.2 M (typ.) RO 0.5 k (typ.)
OSC1 OSC2
RO
OSC1
OSC2
88CS34-205
2003-03-25
TMP88CS34/CP34
(2) Input/Output ports
Port I/O Initial "High-Z" Input/Output Circuitry VDD Remarks Sink open drain output Hysteresis input R R 1k (typ.)
P20
I/O
P30 to P33 P50, P57 P70, P71
Initial "High-Z"
VDD
Tri-state I/O Hysteresis input R 1k (typ.)
I/O Disable R
P34, P35, P51, P52
Open drain output enable I/O
Initial "High-Z"
VDD
Tri-state I/O or Open drain output programmable Hysteresis input R 1k (typ.)
Disable
R
Initial "High-Z" P40 to P47
VDD
Tri-state I/O R 1k (typ.)
I/O Disable R
Initial "High-Z"
VDD
Tri-state I/O Hysteresis input Key-on wake-up input (VIL4 0.65 VDD) R R 1 k (typ.) RA 5 k (typ.) CA 22 pF (typ.)
P53 to P56
I/O
Disable
CA
RA Key-on Wake-up
88CS34-206
2003-03-25
TMP88CS34/CP34
Port
I/O
Input/Output Circuitry VDD Initial "High-Z" Disable R
Remarks Sink open drain input/output High-current output IOL 20 mA (typ.) R 1 k (typ.) RA 5 k (typ.) CA 22 pF (typ.) Key-on wake-up input (VIL4 0.65 VDD) VDD Tri-state input/output R 1 k (typ.) RA 5 k (typ.) CA 22 pF (typ.) Key-on wake-up input (VIL4 0.65 VDD)
P60
I/O
CA
RA Key-on Wake-up
Initial "High-Z"
P61
I/O
Disable
R
CA
RA Key-on Wake-up VDD
Initial "High-Z" P62 to P67
Tri-state input/output R 1k (typ.)
I/O Disable R
88CS34-207
2003-03-25
TMP88CS34/CP34
Electrical Characteristics
Absolute maximum ratings
Parameter Supply Voltage Input Voltage Output Voltage Output Current (Per 1 pin) Symbol VDD VIN VOUT1 IOUT1 IOUT2 Output Current (Total) Power Dissipation [Topr 70 C] IOUT1 IOUT2 PD Tsld Tstg Topr Ports P2, P3, P4, P5, P61 to P67, P7 Ports P60 Ports P2, P3, P4, P5, P64 to P67, P7 Ports P60 (VSS 0 V) Pins Ratings 0.3 to 6.5 0.3 to VDD 0.3 to VDD 3.2 30 mA 30 30 400 260 (10 s) 55 to 125 30 to 70 C mW 0.3 0.3 V Unit
Soldering Temperature (time) Storage Temperature Operating Temperature
Note:
The absolute maximum ratings are rated values which must not be exceeded during operation, even for an instant. Any one of the ratings must not be exceeded. If any absolute maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when designing products which include this device, ensure that no absolute maximum rating value will ever be exceeded.
Recommended operating conditions
Parameter Symbol Pins
(VSS
0 V, Topr
30 to 70 C) Conditions Min Max Unit
fc Supply Voltage VDD VIH1 Input High Voltage VIH2 VIH3 VIL1 Input Low Voltage VIL2 VIL3 fc Clock Frequency fOSC Except hysteresis input Hysteresis input Key-on Wake-up input Except hysteresis input Hysteresis input Key-on Wake-up input XIN, XOUT Internal clock VDD VDD VDD VDD VDD fc
16 MHz NORMAL mode 16 MHz IDLE mode STOP mode VDD 4.5 to 5.5V VDD VDD 4.5 to 5.5V 4.5 to 5.5V 4.5 to 5.5V 4.5 to 5.5V fc fc 8 MHz 16 MHz 8.0 8.0 16.0 0 0.70 0.75 0.90 VDD VDD VDD 0.30 0.25 0.65 MHz VDD V 4.5 5.5
16.0 12.0 24.0
Note 1: The recommended operating conditions for a device are operating conditions under which it can be guaranteed that the device will operate as specified. If the device is used under operating conditions other than the recommended operating conditions (supply voltage, operating temperature range, specified AC/DC values etc.), malfunction may occur. Thus, when designing products which include this device, ensure that the recommended operating conditions for the device are always adhered to. Note 2: Clock frequency fc: Supply voltage range is specified in NORMAL mode and IDLE mode. Note 3: Smaller value is alternatively specified as the maximum value.
88CS34-208
2003-03-25
TMP88CS34/CP34
DC Characteristics
Parameter Hysteresis voltage Symbol VHS IIN1 Input current IIN2 IIN3 IIN4 Input resistance Output leakage current Output high voltage Output low voltage Output low current Supply current in NORMAL mode Supply current in IDLE mode Supply current in STOP mode IDD RIN2 ILO1 ILO2 VOH2 VOL IOL3 Pins Hysteresis inputs TEST Open drain ports Tri-state ports
RESET , STOP RESET
(VSS
0 V, Topr
30 to 70 C) Conditions Min Typ. 0.9 Max Unit V 2 2 2 2 100 220 450 2 2 4.1 V 0.4 20 25 (Note3) 20 0.5 25 10 A 30 mA k A A
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
5.5 V, VIN 5.5 V, VIN 5.5 V, VIN 5.5 V, VIN 5.5 V, VIN 5.5 V, VOUT 5.5 V, VOUT 4.5 V, IOH 4.5 V, IOL 4.5 V, IOL
5.5 V/0 V 5.5 V/0 V 5.5 V/0 V 5.5 V/0 V 0V 5.5 V 5.5 V/0 V 0.7 mA 1.6 mA 1.0 V
Sink open drain ports Tri-state ports Tri-state ports Except XOUT and ports P60 Port P60
VDD 5.5 V fc 16 MHz VIN 5.3 V/0.2 V VDD 5.5 V VIN 5.3 V/0.2 V
Note 1: Typical values show those at Topr
25 C, VDD
5 V.
Note 2: Input Current IIN3; The current through resistor is not included. Note 3: Supply Current IDD; The current (Typ. 0.5 mA) through ladder resistors of ADC is included in NORMAL mode and IDLE mode. AD Conversion Characteristics
Parameter Analog reference voltage Analog reference voltage range Analog input voltage Nonlinearity error Zero point error Full scale error Total error VDD 5.0 V 2 3 Symbol VAREF VASS VAREF VAIN
(VSS
0 V, VDD Conditions
4.5 V to 5.5 V, Topr Min
30 to 70 C) Typ. VDD 0 V VDD Max Unit
supplied from VDD pin. supplied from VSS pin. VDD VSS VSS
VDD 1 2 LSB
Note:
The total error means all error except quanting error.
88CS34-209
2003-03-25
TMP88CS34/CP34
AC characteristics
Parameter Machine cycle time High level clock pulse width Low level clock pulse width Symbol tcy
(VSS
0 V, VDD
4.5 V to 5.5 V, Topr Min 0.5
30 to 70 C) Typ. Max 1.0 Unit s
Conditions In NORMAL mode In IDLE mode
tWCH tWCL
For external clock operation 31.25 (XIN input), fc 16 MHz ns
Recommended oscillating conditions
Parameter High-frequency oscillation Oscillator
(VSS
0 V, VDD
4.5 V to 5.5 V, Topr
30 to 70 C) Recommended Constant
Oscillation Frequency 8 MHz 16 MHz
Recommended Oscillator C1 Murata Murata CSA 8.00MTZ CSA 16.00MXZ040 30 pF 5 pF C2 30 pF 5 pF
Ceramic resonator
XIN
XOUT
C1
C2
High-frequency Oscillation
Note 1: To keep reliable operation, shield the device electrically with the metal plate on its package mold surface against the high electric field, for example, by CRT (Cathode Ray Tube) . Note 2: The product numbers and specifications of the resonators by Murata Manufacturing Co., Ltd. are subject to change. For up-to-date information, please refer to the following URL; http://www.murata.co.jp/search/index.html
88CS34-210
2003-03-25
TMP88CS34/CP34
Recommended oscillating conditions
(VSS
0 V, VDD
4.5 V to 5.5 V, Topr
30 to 70 C)
Item
Oscillation Resonator Frequency 8 MHz 12 MHz
Recommended parameter value L ( H) 33 15 10 6.8 4.7 C1 (pF) 5 to 30 5 to 30 5 to 30 5 to 25 5 to 25 C2 (pF) 10 10 10 10 10
Oscillation for OSD
LC resonator
16 MHz 20 MHz 24 MHz
OSC1 L C1
OSC2
C2
Oscillation for OSD
The frequency generated in LC oscillation can be obtained using the following equations.
f 2 1 ,C LC C1 C2 C1 C2
C1 is not fixed at a constant value. It can be changed to tune into the desired frequency. Note 1: Toshiba's OSD circuit determines a horizontal display start position by counting clock pulses generated in LC oscillation. For this reason, the OSD circuit may fail to detect clock pulses normally, resulting in the horizontal start position becoming unstable, at the beginning of oscillation, if the oscillation amplitude is low. Changing L and C2 from the values recommended for a specific frequency may hamper a stable OSD display. If the LC oscillation frequency is the same as a high-frequency clock value, the oscillation of the high-frequency oscillator may cause the LC oscillation frequency to fluctuate, thus making OSD displays flicker. When determining these parameters, please check the oscillation frequency and the stability of oscillation on your TV sets. Also check the determined parameters on your final products, because the optimum parameter values may vary from one product to another. Note 2: When using the LSI package in a strong electric field, such as near a CRT, electrically shield the package so that its normal operation can be maintained.
88CS34-211
2003-03-25
TMP88CS34/CP34
88CS34-212
2003-03-25

▲Up To Search▲

Price & Availability of TMP88CP34F

	To Download TMP88CP34F Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .